383 lines
6.3 KiB
Plaintext
383 lines
6.3 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 - 2020 Intel Corporation.
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* Copyright (C) 2019 - 2020 Facebook Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Enable ACPI _SWS methods */
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#include <soc/intel/common/acpi/acpi_wake_source.asl>
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Name (_S0, Package (0x04) // mandatory system state
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{
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0x00, 0x00, 0x00, 0x00
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})
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Name (_S5, Package (0x04) // mandatory system state
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{
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0x07, 0x00, 0x00, 0x00
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})
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (DBG0, SystemIO, 0x80, 0x02)
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Field (DBG0, ByteAcc, Lock, Preserve)
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{
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IO80, 8,
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IO81, 8
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}
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/* IO-Trap at 0x800.
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* This is the ACPI->SMI communication interface.
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*/
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OperationRegion (IO_T, SystemIO, 0x800, 0x10)
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Field (IO_T, ByteAcc, NoLock, Preserve)
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{
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Offset (0x8),
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TRP0, 8 /* IO-Trap at 0x808 */
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}
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OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400)
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Field (PSYS, ByteAcc, NoLock, Preserve)
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{
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PLAT, 32, // Platform ID
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// IOAPIC
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APC0, 1, // PCH IOAPIC Enable
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AP00, 1, // PC00 IOAPIC Enable
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AP01, 1, // PC01 IOAPIC Enable
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AP02, 1, // PC02 IOAPIC Enable
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AP03, 1, // PC03 IOAPIC Enable
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AP04, 1, // PC04 IOAPIC Enable
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AP05, 1, // PC05 IOAPIC Enable
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AP06, 1, // PC06 IOAPIC Enable
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AP07, 1, // PC07 IOAPIC Enable
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AP08, 1, // PC08 IOAPIC Enable
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AP09, 1, // PC09 IOAPIC Enable
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AP10, 1, // PC10 IOAPIC Enable
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AP11, 1, // PC11 IOAPIC Enable
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AP12, 1, // PC12 IOAPIC Enable
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AP13, 1, // PC13 IOAPIC Enable
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AP14, 1, // PC14 IOAPIC Enable
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AP15, 1, // PC15 IOAPIC Enable
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AP16, 1, // PC16 IOAPIC Enable
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AP17, 1, // PC17 IOAPIC Enable
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AP18, 1, // PC18 IOAPIC Enable
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AP19, 1, // PC19 IOAPIC Enable
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AP20, 1, // PC20 IOAPIC Enable
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AP21, 1, // PC21 IOAPIC Enable
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AP22, 1, // PC22 IOAPIC Enable
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AP23, 1, // PC23 IOAPIC Enable
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RESA, 7,
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SKOV, 1, // Override Socket APIC Id
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RES0, 7,
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// Power Management
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TPME, 1,
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CSEN, 1,
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C3EN, 1,
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C6EN, 1,
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C7EN, 1,
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MWOS, 1,
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PSEN, 1,
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EMCA, 1,
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HWAL, 2,
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KPRS, 1,
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MPRS, 1,
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TSEN, 1,
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FGTS, 1,
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OSCX, 1,
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RESX, 1,
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// RAS
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CPHP, 8,
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IIOP, 8,
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IIOH, 64,
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PRBM, 32,
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P0ID, 32,
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P1ID, 32,
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P2ID, 32,
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P3ID, 32,
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P4ID, 32,
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P5ID, 32,
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P6ID, 32,
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P7ID, 32,
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P0BM, 64,
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P1BM, 64,
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P2BM, 64,
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P3BM, 64,
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P4BM, 64,
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P5BM, 64,
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P6BM, 64,
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P7BM, 64,
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MEBM, 16,
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MEBC, 16,
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CFMM, 32,
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TSSY, 32, // TODO: This is TSSZ in system booted from production FW
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M0BS, 64,
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M1BS, 64,
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M2BS, 64,
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M3BS, 64,
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M4BS, 64,
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M5BS, 64,
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M6BS, 64,
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M7BS, 64,
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M0RN, 64,
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M1RN, 64,
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M2RN, 64,
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M3RN, 64,
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M4RN, 64,
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M5RN, 64,
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M6RN, 64,
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M7RN, 64,
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SMI0, 32,
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SMI1, 32,
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SMI2, 32,
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SMI3, 32,
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SCI0, 32,
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SCI1, 32,
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SCI2, 32,
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SCI3, 32,
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MADD, 64,
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CUU0, 128,
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CUU1, 128,
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CUU2, 128,
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CUU3, 128,
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CUU4, 128,
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CUU5, 128,
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CUU6, 128,
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CUU7, 128,
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CPSP, 8,
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ME00, 128,
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ME01, 128,
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ME10, 128,
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ME11, 128,
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ME20, 128,
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ME21, 128,
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ME30, 128,
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ME31, 128,
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ME40, 128,
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ME41, 128,
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ME50, 128,
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ME51, 128,
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ME60, 128,
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ME61, 128,
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ME70, 128,
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ME71, 128,
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MESP, 16,
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LDIR, 64,
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PRID, 32,
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AHPE, 8,
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// VTD
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DHRD, 192,
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ATSR, 192,
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RHSA, 192,
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// SR-IOV
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WSIC, 8,
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WSIS, 16,
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WSIB, 8,
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WSID, 8,
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WSIF, 8,
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WSTS, 8,
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WHEA, 8,
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// BIOS Guard
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BGMA, 64,
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BGMS, 8,
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BGIO, 16,
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BGIL, 8,
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CNBS, 8,
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// USB3
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XHMD, 8,
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SBV1, 8,
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SBV2, 8,
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// HWPM
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HWEN, 2,
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ACEN, 1,
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HWPI, 1,
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RES1, 4,
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// IIO
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BB00, 8,
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BB01, 8,
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BB02, 8,
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BB03, 8,
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BB04, 8,
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BB05, 8,
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BB06, 8,
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BB07, 8,
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BB08, 8,
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BB09, 8,
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BB10, 8,
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BB11, 8,
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BB12, 8,
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BB13, 8,
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BB14, 8,
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BB15, 8,
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BB16, 8,
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BB17, 8,
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BB18, 8,
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BB19, 8,
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BB20, 8,
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BB21, 8,
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BB22, 8,
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BB23, 8,
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BB24, 8,
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BB25, 8,
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BB26, 8,
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BB27, 8,
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BB28, 8,
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BB29, 8,
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BB30, 8,
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BB31, 8,
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BB32, 8,
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BB33, 8,
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BB34, 8,
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BB35, 8,
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BB36, 8,
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BB37, 8,
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BB38, 8,
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BB39, 8,
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BB40, 8,
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BB41, 8,
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BB42, 8,
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BB43, 8,
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BB44, 8,
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BB45, 8,
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BB46, 8,
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BB47, 8,
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SGEN, 8,
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SG00, 8,
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SG01, 8,
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SG02, 8,
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SG03, 8,
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SG04, 8,
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SG05, 8,
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SG06, 8,
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SG07, 8,
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// Performance
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CLOD, 8,
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// XTU
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XTUB, 32,
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XTUS, 32,
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XMBA, 32,
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DDRF, 8,
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RT3S, 8,
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RTP0, 8,
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RTP3, 8,
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// FPGA
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FBB0, 8,
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FBB1, 8,
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FBB2, 8,
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FBB3, 8,
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FBB4, 8,
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FBB5, 8,
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FBB6, 8,
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FBB7, 8,
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FBL0, 8,
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FBL1, 8,
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FBL2, 8,
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FBL3, 8,
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FBL4, 8,
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FBL5, 8,
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FBL6, 8,
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FBL7, 8,
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P0FB, 8,
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P1FB, 8,
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P2FB, 8,
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P3FB, 8,
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P4FB, 8,
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P5FB, 8,
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P6FB, 8,
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P7FB, 8,
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FMB0, 32,
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FMB1, 32,
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FMB2, 32,
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FMB3, 32,
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FMB4, 32,
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FMB5, 32,
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FMB6, 32,
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FMB7, 32,
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FML0, 32,
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FML1, 32,
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FML2, 32,
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FML3, 32,
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FML4, 32,
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FML5, 32,
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FML6, 32,
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FML7, 32,
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FKPB, 32,
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FKB0, 8,
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FKB1, 8,
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FKB2, 8,
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FKB3, 8,
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FKB4, 8,
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FKB5, 8,
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FKB6, 8,
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FKB7, 8
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}
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/* SMI I/O Trap */
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Method (TRAP, 1, Serialized)
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{
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Store (Arg0, SMIF) // SMI Function
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Store (0, TRP0) // Generate trap
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Return (SMIF) // Return value of SMI handler
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}
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/*
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* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method (_PIC, 1)
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{
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/* Remember the OS' IRQ routing choice. */
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Store (Arg0, PICM)
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}
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/*
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* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method (_PTS, 1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method (_WAK, 1)
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{
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Return (Package (){ 0, 0 })
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}
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