48 lines
1.1 KiB
C
48 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <superio/smsc/sch5545/sch5545.h>
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#include <superio/smsc/sch5545/sch5545_emi.h>
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#include "sch5545_ec.h"
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 6, 0 },
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{ 1, 6, 0 },
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{ 1, 1, 1 },
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{ 1, 1, 1 },
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{ 1, 1, 2 },
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{ 1, 1, 2 },
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{ 1, 6, 3 },
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{ 1, 6, 3 },
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{ 1, 6, 4 },
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{ 1, 6, 4 },
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{ 1, 6, 5 },
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{ 1, 1, 5 },
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{ 1, 1, 6 },
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{ 1, 6, 6 },
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};
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void bootblock_mainboard_early_init(void)
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{
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/*
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* FIXME: the board gets stuck in reset loop in
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* mainboard_romstage_entry. Avoid that by clearing SSKPD
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*/
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pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
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pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32);
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MCHBAR16(SSKPD_HI) = 0;
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sch5545_early_init(0x2e);
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/* Bare EC and SIO GPIO initialization which allows to enable serial port */
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sch5545_emi_init(0x2e);
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sch5545_emi_disable_interrupts();
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sch5545_ec_early_init();
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if (CONFIG(CONSOLE_SERIAL))
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sch5545_enable_uart(0x2e, 0);
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}
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