161 lines
4.8 KiB
C
161 lines
4.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <drivers/ipmi/ipmi_kcs.h>
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#include <drivers/ipmi/ocp/ipmi_ocp.h>
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#include <drivers/vpd/vpd.h>
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#include <fsp/api.h>
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#include <FspmUpd.h>
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#include <soc/romstage.h>
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#include "chip.h"
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#include "ipmi.h"
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#include "vpd.h"
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/*
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* Search from VPD_RW first then VPD_RO for UPD config variables,
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* overwrites them from VPD if it's found.
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*/
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static void mainboard_config_upd(FSPM_UPD *mupd)
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{
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uint8_t val;
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int val_int;
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/* Send FSP log message to SOL */
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if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val))
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mupd->FspmConfig.SerialIoUartDebugEnable = val;
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else {
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printk(BIOS_INFO, "Not able to get VPD %s, default set "
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"SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT);
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mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT;
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}
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mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8;
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if (mupd->FspmConfig.SerialIoUartDebugEnable) {
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/* FSP debug log level */
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if (vpd_get_int(FSP_LOG_LEVEL, VPD_RW_THEN_RO, &val_int)) {
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if (val_int < 0 || val_int > 0x0f) {
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printk(BIOS_DEBUG, "Invalid DebugPrintLevel value from VPD: "
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"%d\n", val_int);
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val_int = FSP_LOG_LEVEL_DEFAULT;
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}
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printk(BIOS_DEBUG, "Setting DebugPrintLevel %d from VPD\n", val_int);
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mupd->FspmConfig.DebugPrintLevel = (uint8_t)val_int;
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} else {
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printk(BIOS_INFO, "Not able to get VPD %s, default set "
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"DebugPrintLevel to %d\n", FSP_LOG_LEVEL,
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FSP_LOG_LEVEL_DEFAULT);
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mupd->FspmConfig.DebugPrintLevel = FSP_LOG_LEVEL_DEFAULT;
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}
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}
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/* Enable DCI */
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if (vpd_get_bool(FSP_DCI, VPD_RW_THEN_RO, &val)) {
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printk(BIOS_DEBUG, "Setting DciEn %d from VPD\n", val);
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mupd->FspmConfig.PchDciEn = val;
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} else {
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printk(BIOS_INFO, "Not able to get VPD %s, default set "
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"DciEn to %d\n", FSP_DCI, FSP_DCI_DEFAULT);
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mupd->FspmConfig.PchDciEn = FSP_DCI_DEFAULT;
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}
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/*
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* UnusedUpdSpace0[0] is reserved for Memory Refresh Watermark.
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* Following code is effective when MemRefreshWaterMark patch is added to FSP
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* and when corresponding VPD variable is set.
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*/
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if (vpd_get_int(FSPM_MEMREFRESHWATERMARK, VPD_RW_THEN_RO, &val_int)) {
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if (val_int < 0 || val_int > 2) {
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printk(BIOS_DEBUG, "Invalid MemRefreshWatermark value from VPD: "
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"%d\n", val_int);
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val_int = FSPM_MEMREFRESHWATERMARK_DEFAULT;
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}
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printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val_int);
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mupd->FspmConfig.UnusedUpdSpace0[0] = (uint8_t)val_int;
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}
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}
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/* Update bifurcation settings according to different Configs */
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static void oem_update_iio(FSPM_UPD *mupd)
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{
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uint8_t pcie_config = 0;
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/* Default set to PCIE_CONFIG_C first */
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mupd->FspmConfig.IioConfigIOU0[0] = IIO_BIFURCATE_x4x4x4x4;
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mupd->FspmConfig.IioConfigIOU1[0] = IIO_BIFURCATE_x4x4x4x4;
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mupd->FspmConfig.IioConfigIOU2[0] = IIO_BIFURCATE_xxxxxxxx;
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mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_xxxxxx16;
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mupd->FspmConfig.IioConfigIOU4[0] = IIO_BIFURCATE_xxxxxxxx;
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/* Update IIO bifurcation according to different Configs */
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if (ipmi_get_pcie_config(&pcie_config) == CB_SUCCESS) {
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printk(BIOS_DEBUG, "get IPMI PCIe config: %d\n", pcie_config);
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switch (pcie_config) {
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case PCIE_CONFIG_A:
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mupd->FspmConfig.IioConfigIOU0[0] = IIO_BIFURCATE_xxxxxxxx;
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mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_xxxxxxxx;
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break;
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case PCIE_CONFIG_B:
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mupd->FspmConfig.IioConfigIOU0[0] = IIO_BIFURCATE_xxxxxxxx;
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mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_x4x4x4x4;
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break;
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case PCIE_CONFIG_D:
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mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_x4x4x4x4;
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break;
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case PCIE_CONFIG_C:
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default:
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break;
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}
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} else {
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printk(BIOS_ERR, "%s failed to get IPMI PCIe config\n", __func__);
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}
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}
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/*
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* Configure GPIO depend on platform
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*/
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static void mainboard_config_gpios(FSPM_UPD *mupd)
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{
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/* To be implemented */
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}
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static void mainboard_config_iio(FSPM_UPD *mupd)
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{
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uint8_t index;
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const config_t *config = config_of_soc();
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oem_update_iio(mupd);
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for (index = 0; index < MAX_PCH_PCIE_PORT; index++) {
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mupd->FspmConfig.PchPcieForceEnable[index] =
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config->pch_pci_port[index].ForceEnable;
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mupd->FspmConfig.PchPciePortLinkSpeed[index] =
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config->pch_pci_port[index].PortLinkSpeed;
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}
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mupd->FspmConfig.PchPcieRootPortFunctionSwap = 0x00;
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/* The default value is 0XFF in FSP, set it to 0xFE by platform */
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mupd->FspmConfig.PchPciePllSsc = 0xFE;
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}
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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/* Since it's the first IPMI command, it's better to run get BMC
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selftest result first */
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if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) {
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ipmi_set_post_start(CONFIG_BMC_KCS_BASE);
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init_frb2_wdt();
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}
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mainboard_config_gpios(mupd);
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mainboard_config_iio(mupd);
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mainboard_config_upd(mupd);
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}
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void mainboard_rtc_failed(void)
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{
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if (ipmi_set_cmos_clear() == CB_SUCCESS)
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printk(BIOS_DEBUG, "%s: IPMI set cmos clear successful\n", __func__);
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else
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printk(BIOS_ERR, "%s: IPMI set cmos clear failed\n", __func__);
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}
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