3357 lines
106 KiB
C
3357 lines
106 KiB
C
/** @file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPMUPD_H__
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#define __FSPMUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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#include <MemInfoHob.h>
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///
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/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
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///
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typedef struct {
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UINT8 Revision; ///< Chipset Init Info Revision
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UINT8 Rsvd[3]; ///< Reserved
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UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
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UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
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} CHIPSET_INIT_INFO;
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/** Fsp M Configuration
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**/
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typedef struct {
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/** Offset 0x0040 - Platform Reserved Memory Size
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The minimum platform memory size required to pass control into DXE
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**/
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UINT64 PlatformMemorySize;
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/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0
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Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
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**/
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UINT32 MemorySpdPtr00;
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/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1
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Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
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**/
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UINT32 MemorySpdPtr01;
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/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0
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Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
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**/
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UINT32 MemorySpdPtr10;
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/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1
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Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
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**/
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UINT32 MemorySpdPtr11;
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/** Offset 0x0058 - SPD Data Length
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Length of SPD Data
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0x100:256 Bytes, 0x200:512 Bytes
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**/
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UINT16 MemorySpdDataLen;
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/** Offset 0x005A - Dq Byte Map CH0
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Dq byte mapping between CPU and DRAM, Channel 0: board-dependent
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**/
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UINT8 DqByteMapCh0[12];
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/** Offset 0x0066 - Dq Byte Map CH1
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Dq byte mapping between CPU and DRAM, Channel 1: board-dependent
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**/
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UINT8 DqByteMapCh1[12];
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/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0
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Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
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**/
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UINT8 DqsMapCpu2DramCh0[8];
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/** Offset 0x007A - Dqs Map CPU to DRAM CH 1
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Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
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**/
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UINT8 DqsMapCpu2DramCh1[8];
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/** Offset 0x0082 - RcompResister settings
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Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design
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Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide
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the appropriate values.
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**/
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UINT16 RcompResistor[3];
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/** Offset 0x0088 - RcompTarget settings
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RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines,
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otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values.
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**/
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UINT16 RcompTarget[5];
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/** Offset 0x0092 - Dqs Pins Interleaved Setting
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Indicates DqPinsInterleaved setting: board-dependent
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$EN_DIS
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**/
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UINT8 DqPinsInterleaved;
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/** Offset 0x0093 - VREF_CA
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CA Vref routing: board-dependent
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0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,
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2:VREF_CA to CH_A and VREF_DQ_B to CH_B
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**/
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UINT8 CaVrefConfig;
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/** Offset 0x0094 - Smram Mask
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The SMM Regions AB-SEG and/or H-SEG reserved
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0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
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**/
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UINT8 SmramMask;
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/** Offset 0x0095 - MRC Fast Boot
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Enables/Disable the MRC fast path thru the MRC
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$EN_DIS
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**/
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UINT8 MrcFastBoot;
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/** Offset 0x0096 - Rank Margin Tool per Task
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This option enables the user to execute Rank Margin Tool per major training step
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in the MRC.
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$EN_DIS
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**/
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UINT8 RmtPerTask;
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/** Offset 0x0097 - Training Trace
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This option enables the trained state tracing feature in MRC. This feature will
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print out the key training parameters state across major training steps.
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$EN_DIS
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**/
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UINT8 TrainTrace;
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/** Offset 0x0098 - Intel Enhanced Debug
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Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
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0 : Disable, 0x400000 : Enable
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**/
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UINT32 IedSize;
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/** Offset 0x009C - Tseg Size
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Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
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0x0400000:4MB, 0x01000000:16MB
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**/
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UINT32 TsegSize;
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/** Offset 0x00A0 - MMIO Size
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Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
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**/
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UINT16 MmioSize;
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/** Offset 0x00A2 - Probeless Trace
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Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
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This also requires IED to be enabled.
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$EN_DIS
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**/
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UINT8 ProbelessTrace;
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/** Offset 0x00A3
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**/
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UINT8 UnusedUpdSpace0[2];
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/** Offset 0x00A5 - Enable SMBus
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Enable/disable SMBus controller.
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$EN_DIS
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**/
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UINT8 SmbusEnable;
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/** Offset 0x00A6 - Spd Address Tabl
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Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
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if SPD Address is 00
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**/
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UINT8 SpdAddressTable[4];
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/** Offset 0x00AA - Platform Debug Consent
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To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
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Enabling this BIOS option may alter the default value of other debug-related BIOS
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options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC]
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have the same setting
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0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),
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4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC)
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**/
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UINT8 PlatformDebugConsent;
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/** Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support
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This BIOS option enables kernel and platform debug for USB3 interface over a UFP
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Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
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0:Disabled, 1:Enabled, 2:No Change
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**/
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UINT8 DciUsb3TypecUfpDbg;
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/** Offset 0x00AC - PCH Trace Hub Mode
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Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
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if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
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0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
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**/
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UINT8 PchTraceHubMode;
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/** Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size
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Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,
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128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
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0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
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**/
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UINT8 PchTraceHubMemReg0Size;
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/** Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size
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Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,
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128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
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0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
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**/
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UINT8 PchTraceHubMemReg1Size;
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/** Offset 0x00AF - PchPreMemRsvd
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Reserved for PCH Pre-Mem Reserved
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$EN_DIS
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**/
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UINT8 PchPreMemRsvd[9];
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/** Offset 0x00B8 - Internal Graphics Pre-allocated Memory
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Size of memory preallocated for internal graphics.
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0x00:0MB, 0x01:32MB, 0x02:64MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB,
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0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB,
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0xFD:56MB, 0xFE:60MB
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**/
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UINT8 IgdDvmt50PreAlloc;
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/** Offset 0x00B9 - Internal Graphics
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Enable/disable internal graphics.
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$EN_DIS
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**/
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UINT8 InternalGfx;
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/** Offset 0x00BA - Aperture Size
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Select the Aperture Size.
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0:128 MB, 1:256 MB, 2:512 MB
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**/
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UINT8 ApertureSize;
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/** Offset 0x00BB - Board Type
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MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
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Halo, 7=UP Server
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0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
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**/
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UINT8 UserBd;
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/** Offset 0x00BC - SA GV
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System Agent dynamic frequency support and when enabled memory will be training
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at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
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2=FixedMid, 3=FixedHigh, and 4=Enabled.
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0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled
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**/
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UINT8 SaGv;
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/** Offset 0x00BD
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**/
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UINT8 UnusedUpdSpace1;
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/** Offset 0x00BE - DDR Frequency Limit
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Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
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2133, 2400, 2667, 2933 and 0 for Auto.
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1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
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**/
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UINT16 DdrFreqLimit;
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/** Offset 0x00C0 - Low Frequency
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SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
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2400, 2667, 2933 and 0 for Auto.
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1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
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**/
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UINT16 FreqSaGvLow;
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/** Offset 0x00C2 - Mid Frequency
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SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
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2400, 2667, 2933 and 0 for Auto.
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1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
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**/
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UINT16 FreqSaGvMid;
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/** Offset 0x00C4 - Rank Margin Tool
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Enable/disable Rank Margin Tool.
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$EN_DIS
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**/
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UINT8 RMT;
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/** Offset 0x00C5 - Channel A DIMM Control
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Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.
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0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
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**/
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UINT8 DisableDimmChannel0;
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/** Offset 0x00C6 - Channel B DIMM Control
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Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.
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0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
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**/
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UINT8 DisableDimmChannel1;
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/** Offset 0x00C7 - Scrambler Support
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This option enables data scrambling in memory.
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$EN_DIS
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**/
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UINT8 ScramblerSupport;
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/** Offset 0x00C8 - EV Loader Test Content Pointer
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Pointer to EV Loader Test Content in Memory
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**/
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UINT32 EvTestContentPtr;
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/** Offset 0x00CC - EV Loader Test Content Size
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Size of EV Loader Test Content in Memory
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**/
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UINT32 EvTestContentSize;
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/** Offset 0x00D0 - EV Loader Test Config Pointer
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Pointer to EV Loader Test Config in Memory
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**/
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UINT32 EvTestConfigPtr;
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/** Offset 0x00D4 - EV Loader Test Config Size
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Size of EV Loader Test Config in Memory
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**/
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UINT32 EvTestConfigSize;
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/** Offset 0x00D8 - SPD Profile Selected
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Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
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Profile 1, 3=XMP Profile 2
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0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2
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**/
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UINT8 SpdProfileSelected;
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/** Offset 0x00D9 - Memory Reference Clock
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100MHz, 133MHz.
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0:133MHz, 1:100MHz
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**/
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UINT8 RefClk;
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/** Offset 0x00DA - Memory Voltage
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Memory Voltage Override (Vddq). Default = no override
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0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
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Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
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**/
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UINT16 VddVoltage;
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/** Offset 0x00DC - Memory Ratio
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Automatic or the frequency will equal ratio times reference clock. Set to Auto to
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recalculate memory timings listed below.
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0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
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**/
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UINT8 Ratio;
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/** Offset 0x00DD - QCLK Odd Ratio
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Adds 133 or 100 MHz to QCLK frequency, depending on RefClk
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$EN_DIS
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**/
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UINT8 OddRatioMode;
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/** Offset 0x00DE - tCL
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CAS Latency, 0: AUTO, max: 31
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**/
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UINT8 tCL;
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/** Offset 0x00DF - tCWL
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Min CAS Write Latency Delay Time, 0: AUTO, max: 34
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**/
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UINT8 tCWL;
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/** Offset 0x00E0 - tRCD/tRP
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RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
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**/
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UINT8 tRCDtRP;
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/** Offset 0x00E1 - tRRD
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Min Row Active to Row Active Delay Time, 0: AUTO, max: 15
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**/
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UINT8 tRRD;
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/** Offset 0x00E2 - tFAW
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Min Four Activate Window Delay Time, 0: AUTO, max: 63
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**/
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UINT16 tFAW;
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/** Offset 0x00E4 - tRAS
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RAS Active Time, 0: AUTO, max: 64
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**/
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UINT16 tRAS;
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/** Offset 0x00E6 - tREFI
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Refresh Interval, 0: AUTO, max: 65535
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**/
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UINT16 tREFI;
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/** Offset 0x00E8 - tRFC
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Min Refresh Recovery Delay Time, 0: AUTO, max: 1023
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**/
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UINT16 tRFC;
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/** Offset 0x00EA - tRTP
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Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
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values: 5, 6, 7, 8, 9, 10, 12
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**/
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UINT8 tRTP;
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/** Offset 0x00EB - tWR
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Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
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20, 24, 30, 34, 40
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0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
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34:34, 40:40
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**/
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UINT8 tWR;
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/** Offset 0x00EC - tWTR
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Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28
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**/
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UINT8 tWTR;
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/** Offset 0x00ED - NMode
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System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
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**/
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UINT8 NModeSupport;
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/** Offset 0x00EE - DllBwEn[0]
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DllBwEn[0], for 1067 (0..7)
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**/
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UINT8 DllBwEn0;
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/** Offset 0x00EF - DllBwEn[1]
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DllBwEn[1], for 1333 (0..7)
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**/
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UINT8 DllBwEn1;
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/** Offset 0x00F0 - DllBwEn[2]
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DllBwEn[2], for 1600 (0..7)
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**/
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UINT8 DllBwEn2;
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/** Offset 0x00F1 - DllBwEn[3]
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DllBwEn[3], for 1867 and up (0..7)
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**/
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UINT8 DllBwEn3;
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/** Offset 0x00F2 - ISVT IO Port Address
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ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default
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**/
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UINT8 IsvtIoPort;
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/** Offset 0x00F3 - CPU Trace Hub Mode
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Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable'
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trace hub functionality.
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0: Disable, 1:Target Debugger Mode
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**/
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UINT8 CpuTraceHubMode;
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/** Offset 0x00F4 - CPU Trace Hub Memory Region 0
|
|
CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
|
|
128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
|
|
0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
|
|
**/
|
|
UINT8 CpuTraceHubMemReg0Size;
|
|
|
|
/** Offset 0x00F5 - CPU Trace Hub Memory Region 1
|
|
CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
|
|
128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
|
|
0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
|
|
**/
|
|
UINT8 CpuTraceHubMemReg1Size;
|
|
|
|
/** Offset 0x00F6
|
|
**/
|
|
UINT8 UnusedUpdSpace2[6];
|
|
|
|
/** Offset 0x00FC - Enable Intel HD Audio (Azalia)
|
|
0: Disable, 1: Enable (Default) Azalia controller
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PchHdaEnable;
|
|
|
|
/** Offset 0x00FD - Enable PCH ISH Controller
|
|
0: Disable, 1: Enable (Default) ISH Controller
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PchIshEnable;
|
|
|
|
/** Offset 0x00FE - HECI Timeouts
|
|
0: Disable, 1: Enable (Default) timeout check for HECI
|
|
$EN_DIS
|
|
**/
|
|
UINT8 HeciTimeouts;
|
|
|
|
/** Offset 0x00FF
|
|
**/
|
|
UINT8 UnusedUpdSpace3;
|
|
|
|
/** Offset 0x0100 - HECI1 BAR address
|
|
BAR address of HECI1
|
|
**/
|
|
UINT32 Heci1BarAddress;
|
|
|
|
/** Offset 0x0104 - HECI2 BAR address
|
|
BAR address of HECI2
|
|
**/
|
|
UINT32 Heci2BarAddress;
|
|
|
|
/** Offset 0x0108 - HECI3 BAR address
|
|
BAR address of HECI3
|
|
**/
|
|
UINT32 Heci3BarAddress;
|
|
|
|
/** Offset 0x010C - SG dGPU Power Delay
|
|
SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
|
|
300=300 microseconds
|
|
**/
|
|
UINT16 SgDelayAfterPwrEn;
|
|
|
|
/** Offset 0x010E - SG dGPU Reset Delay
|
|
SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
|
|
microseconds
|
|
**/
|
|
UINT16 SgDelayAfterHoldReset;
|
|
|
|
/** Offset 0x0110 - MMIO size adjustment for AUTO mode
|
|
Positive number means increasing MMIO size, Negative value means decreasing MMIO
|
|
size: 0 (Default)=no change to AUTO mode MMIO size
|
|
**/
|
|
UINT16 MmioSizeAdjustment;
|
|
|
|
/** Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
|
|
Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
|
|
Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
|
|
$EN_DIS
|
|
**/
|
|
UINT8 DmiGen3ProgramStaticEq;
|
|
|
|
/** Offset 0x0113 - Enable/Disable PEG 0
|
|
Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
|
|
it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
|
|
0:Disable, 1:Enable, 2:AUTO
|
|
**/
|
|
UINT8 Peg0Enable;
|
|
|
|
/** Offset 0x0114 - Enable/Disable PEG 1
|
|
Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
|
|
it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
|
|
0:Disable, 1:Enable, 2:AUTO
|
|
**/
|
|
UINT8 Peg1Enable;
|
|
|
|
/** Offset 0x0115 - Enable/Disable PEG 2
|
|
Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
|
|
it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
|
|
0:Disable, 1:Enable, 2:AUTO
|
|
**/
|
|
UINT8 Peg2Enable;
|
|
|
|
/** Offset 0x0116 - Enable/Disable PEG 3
|
|
Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
|
|
it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
|
|
0:Disable, 1:Enable, 2:AUTO
|
|
**/
|
|
UINT8 Peg3Enable;
|
|
|
|
/** Offset 0x0117 - PEG 0 Max Link Speed
|
|
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
|
|
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
|
|
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
|
|
**/
|
|
UINT8 Peg0MaxLinkSpeed;
|
|
|
|
/** Offset 0x0118 - PEG 1 Max Link Speed
|
|
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
|
|
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
|
|
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
|
|
**/
|
|
UINT8 Peg1MaxLinkSpeed;
|
|
|
|
/** Offset 0x0119 - PEG 2 Max Link Speed
|
|
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
|
|
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
|
|
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
|
|
**/
|
|
UINT8 Peg2MaxLinkSpeed;
|
|
|
|
/** Offset 0x011A - PEG 3 Max Link Speed
|
|
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
|
|
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
|
|
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
|
|
**/
|
|
UINT8 Peg3MaxLinkSpeed;
|
|
|
|
/** Offset 0x011B - PEG 0 Max Link Width
|
|
Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
|
|
Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8
|
|
0:Auto, 1:x1, 2:x2, 3:x4, 4:x8
|
|
**/
|
|
UINT8 Peg0MaxLinkWidth;
|
|
|
|
/** Offset 0x011C - PEG 1 Max Link Width
|
|
Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
|
|
Limit Link to x2, (0x3):Limit Link to x4
|
|
0:Auto, 1:x1, 2:x2, 3:x4
|
|
**/
|
|
UINT8 Peg1MaxLinkWidth;
|
|
|
|
/** Offset 0x011D - PEG 2 Max Link Width
|
|
Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
|
|
Limit Link to x2
|
|
0:Auto, 1:x1, 2:x2
|
|
**/
|
|
UINT8 Peg2MaxLinkWidth;
|
|
|
|
/** Offset 0x011E - PEG 3 Max Link Width
|
|
Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
|
|
Limit Link to x2
|
|
0:Auto, 1:x1, 2:x2
|
|
**/
|
|
UINT8 Peg3MaxLinkWidth;
|
|
|
|
/** Offset 0x011F - Power down unused lanes on PEG 0
|
|
(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
|
|
on the max possible link width
|
|
0:No power saving, 1:Auto
|
|
**/
|
|
UINT8 Peg0PowerDownUnusedLanes;
|
|
|
|
/** Offset 0x0120 - Power down unused lanes on PEG 1
|
|
(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
|
|
on the max possible link width
|
|
0:No power saving, 1:Auto
|
|
**/
|
|
UINT8 Peg1PowerDownUnusedLanes;
|
|
|
|
/** Offset 0x0121 - Power down unused lanes on PEG 2
|
|
(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
|
|
on the max possible link width
|
|
0:No power saving, 1:Auto
|
|
**/
|
|
UINT8 Peg2PowerDownUnusedLanes;
|
|
|
|
/** Offset 0x0122 - Power down unused lanes on PEG 3
|
|
(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
|
|
on the max possible link width
|
|
0:No power saving, 1:Auto
|
|
**/
|
|
UINT8 Peg3PowerDownUnusedLanes;
|
|
|
|
/** Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom
|
|
Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
|
|
Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
|
|
Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
|
|
0:Before, 1:After
|
|
**/
|
|
UINT8 InitPcieAspmAfterOprom;
|
|
|
|
/** Offset 0x0124 - PCIe Disable Spread Spectrum Clocking
|
|
PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled,
|
|
Disable SSC(0X1) - Disable SSC per platform design or for compliance testing
|
|
0:Normal Operation, 1:Disable SSC
|
|
**/
|
|
UINT8 PegDisableSpreadSpectrumClocking;
|
|
|
|
/** Offset 0x0125
|
|
**/
|
|
UINT8 UnusedUpdSpace4[3];
|
|
|
|
/** Offset 0x0128 - DMI Gen3 Root port preset values per lane
|
|
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
|
|
**/
|
|
UINT8 DmiGen3RootPortPreset[8];
|
|
|
|
/** Offset 0x0130 - DMI Gen3 End port preset values per lane
|
|
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
|
|
**/
|
|
UINT8 DmiGen3EndPointPreset[8];
|
|
|
|
/** Offset 0x0138 - DMI Gen3 End port Hint values per lane
|
|
Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
|
|
**/
|
|
UINT8 DmiGen3EndPointHint[8];
|
|
|
|
/** Offset 0x0140 - DMI Gen3 RxCTLEp per-Bundle control
|
|
Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
|
|
**/
|
|
UINT8 DmiGen3RxCtlePeaking[4];
|
|
|
|
/** Offset 0x0144
|
|
**/
|
|
UINT8 UnusedUpdSpace5[4];
|
|
|
|
/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control
|
|
Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
|
|
**/
|
|
UINT8 PegGen3RxCtlePeaking[10];
|
|
|
|
/** Offset 0x0152 - Memory data pointer for saved preset search results
|
|
The reference code will store the Gen3 Preset Search results in the SaDataHob's
|
|
PegData structure (SA_PEG_DATA) and platform code can save/restore this data to
|
|
skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0
|
|
**/
|
|
UINT32 PegDataPtr;
|
|
|
|
/** Offset 0x0156 - PEG PERST# GPIO information
|
|
The reference code will use the information in this structure in order to reset
|
|
PCIe Gen3 devices during equalization, if necessary
|
|
**/
|
|
UINT8 PegGpioData[28];
|
|
|
|
/** Offset 0x0172 - PCIe Hot Plug Enable/Disable per port
|
|
0(Default): Disable, 1: Enable
|
|
**/
|
|
UINT8 PegRootPortHPE[4];
|
|
|
|
/** Offset 0x0176 - DeEmphasis control for DMI
|
|
DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
|
|
0: -6dB, 1: -3.5dB
|
|
**/
|
|
UINT8 DmiDeEmphasis;
|
|
|
|
/** Offset 0x0177 - Selection of the primary display device
|
|
0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics
|
|
0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics
|
|
**/
|
|
UINT8 PrimaryDisplay;
|
|
|
|
/** Offset 0x0178 - Selection of iGFX GTT Memory size
|
|
1=2MB, 2=4MB, 3=8MB, Default is 3
|
|
1:2MB, 2:4MB, 3:8MB
|
|
**/
|
|
UINT16 GttSize;
|
|
|
|
/** Offset 0x017A - Temporary MMIO address for GMADR
|
|
The reference code will use this as Temporary MMIO address space to access GMADR
|
|
Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
|
|
(GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress
|
|
- 0x1) (Where ApertureSize = 256MB)
|
|
**/
|
|
UINT32 GmAdr;
|
|
|
|
/** Offset 0x017E - Temporary MMIO address for GTTMMADR
|
|
The reference code will use this as Temporary MMIO address space to access GTTMMADR
|
|
Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
|
|
to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
|
|
+ 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
|
|
**/
|
|
UINT32 GttMmAdr;
|
|
|
|
/** Offset 0x0182 - Selection of PSMI Region size
|
|
0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
|
|
0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
|
|
**/
|
|
UINT8 PsmiRegionSize;
|
|
|
|
/** Offset 0x0183 - Switchable Graphics GPIO information for PEG 0
|
|
Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
|
|
**/
|
|
UINT8 SaRtd3Pcie0Gpio[24];
|
|
|
|
/** Offset 0x019B - Switchable Graphics GPIO information for PEG 1
|
|
Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
|
|
**/
|
|
UINT8 SaRtd3Pcie1Gpio[24];
|
|
|
|
/** Offset 0x01B3 - Switchable Graphics GPIO information for PEG 2
|
|
Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
|
|
**/
|
|
UINT8 SaRtd3Pcie2Gpio[24];
|
|
|
|
/** Offset 0x01CB - Switchable Graphics GPIO information for PEG 3
|
|
Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs
|
|
**/
|
|
UINT8 SaRtd3Pcie3Gpio[24];
|
|
|
|
/** Offset 0x01E3 - Enable/Disable MRC TXT dependency
|
|
When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
|
|
MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
|
|
$EN_DIS
|
|
**/
|
|
UINT8 TxtImplemented;
|
|
|
|
/** Offset 0x01E4 - Enable/Disable SA OcSupport
|
|
Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SaOcSupport;
|
|
|
|
/** Offset 0x01E5 - GT slice Voltage Mode
|
|
0(Default): Adaptive, 1: Override
|
|
0: Adaptive, 1: Override
|
|
**/
|
|
UINT8 GtVoltageMode;
|
|
|
|
/** Offset 0x01E6 - Maximum GTs turbo ratio override
|
|
0(Default)=Minimal/Auto, 60=Maximum
|
|
**/
|
|
UINT8 GtMaxOcRatio;
|
|
|
|
/** Offset 0x01E7 - The voltage offset applied to GT slice
|
|
0(Default)=Minimal, 1000=Maximum
|
|
**/
|
|
UINT16 GtVoltageOffset;
|
|
|
|
/** Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies
|
|
0(Default)=Minimal, 2000=Maximum
|
|
**/
|
|
UINT16 GtVoltageOverride;
|
|
|
|
/** Offset 0x01EB - adaptive voltage applied during turbo frequencies
|
|
0(Default)=Minimal, 2000=Maximum
|
|
**/
|
|
UINT16 GtExtraTurboVoltage;
|
|
|
|
/** Offset 0x01ED - voltage offset applied to the SA
|
|
0(Default)=Minimal, 1000=Maximum
|
|
**/
|
|
UINT16 SaVoltageOffset;
|
|
|
|
/** Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU
|
|
Root port Index number to indicate which PCIe root port has dGPU
|
|
**/
|
|
UINT8 RootPortIndex;
|
|
|
|
/** Offset 0x01F0 - Realtime Memory Timing
|
|
0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
|
|
realtime memory timing changes after MRC_DONE.
|
|
0: Disabled, 1: Enabled
|
|
**/
|
|
UINT8 RealtimeMemoryTiming;
|
|
|
|
/** Offset 0x01F1 - Enable/Disable SA IPU
|
|
Enable(Default): Enable SA IPU, Disable: Disable SA IPU
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SaIpuEnable;
|
|
|
|
/** Offset 0x01F2 - IPU IMR Configuration
|
|
0:IPU Camera, 1:IPU Gen Default is 0
|
|
0:IPU Camera, 1:IPU Gen
|
|
**/
|
|
UINT8 SaIpuImrConfiguration;
|
|
|
|
/** Offset 0x01F3 - Selection of PSMI Support On/Off
|
|
0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
|
|
$EN_DIS
|
|
**/
|
|
UINT8 GtPsmiSupport;
|
|
|
|
/** Offset 0x01F4 - SaPreMemProductionRsvd
|
|
Reserved for SA Pre-Mem Production
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SaPreMemProductionRsvd[12];
|
|
|
|
/** Offset 0x0200 - BIST on Reset
|
|
Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 BistOnReset;
|
|
|
|
/** Offset 0x0201 - Skip Stop PBET Timer Enable/Disable
|
|
Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SkipStopPbet;
|
|
|
|
/** Offset 0x0202 - C6DRAM power gating feature
|
|
This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
|
|
power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
|
|
feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EnableC6Dram;
|
|
|
|
/** Offset 0x0203 - Over clocking support
|
|
Over clocking support; <b>0: Disable</b>; 1: Enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 OcSupport;
|
|
|
|
/** Offset 0x0204 - Over clocking Lock
|
|
Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 OcLock;
|
|
|
|
/** Offset 0x0205 - Maximum Core Turbo Ratio Override
|
|
Maximum core turbo ratio override allows to increase CPU core frequency beyond the
|
|
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83
|
|
**/
|
|
UINT8 CoreMaxOcRatio;
|
|
|
|
/** Offset 0x0206 - Core voltage mode
|
|
Core voltage mode; <b>0: Adaptive</b>; 1: Override.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 CoreVoltageMode;
|
|
|
|
/** Offset 0x0207 - Minimum clr turbo ratio override
|
|
Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-83
|
|
**/
|
|
UINT8 RingMinOcRatio;
|
|
|
|
/** Offset 0x0208 - Maximum clr turbo ratio override
|
|
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
|
|
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83
|
|
**/
|
|
UINT8 RingMaxOcRatio;
|
|
|
|
/** Offset 0x0209 - Hyper Threading Enable/Disable
|
|
Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
|
|
$EN_DIS
|
|
**/
|
|
UINT8 HyperThreading;
|
|
|
|
/** Offset 0x020A - CPU ratio value
|
|
CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled.
|
|
**/
|
|
UINT8 CpuRatio;
|
|
|
|
/** Offset 0x020B - Boot frequency
|
|
Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-
|
|
<b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo
|
|
is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
|
|
0:0, 1:1, 2:2
|
|
**/
|
|
UINT8 BootFrequency;
|
|
|
|
/** Offset 0x020C - Number of active cores
|
|
Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
|
|
2 </b>;<b>3: 3 </b>
|
|
0:All, 1:1, 2:2, 3:3
|
|
**/
|
|
UINT8 ActiveCoreCount;
|
|
|
|
/** Offset 0x020D - Processor Early Power On Configuration FCLK setting
|
|
<b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
|
|
2: 400 MHz. - 3: Reserved
|
|
0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
|
|
**/
|
|
UINT8 FClkFrequency;
|
|
|
|
/** Offset 0x020E - Set JTAG power in C10 and deeper power states
|
|
False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
|
|
and deeper power states for debug purpose. <b>0: False</b>; 1: True.
|
|
0: False, 1: True
|
|
**/
|
|
UINT8 JtagC10PowerGateDisable;
|
|
|
|
/** Offset 0x020F - Enable or Disable VMX
|
|
Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 VmxEnable;
|
|
|
|
/** Offset 0x0210 - AVX2 Ratio Offset
|
|
0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
|
|
vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
|
|
**/
|
|
UINT8 Avx2RatioOffset;
|
|
|
|
/** Offset 0x0211 - AVX3 Ratio Offset
|
|
0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
|
|
vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
|
|
**/
|
|
UINT8 Avx3RatioOffset;
|
|
|
|
/** Offset 0x0212 - BCLK Adaptive Voltage Enable
|
|
When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
|
|
Disable;<b> 1: Enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 BclkAdaptiveVoltage;
|
|
|
|
/** Offset 0x0213 - Core PLL voltage offset
|
|
Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
|
|
**/
|
|
UINT8 CorePllVoltageOffset;
|
|
|
|
/** Offset 0x0214 - core voltage override
|
|
The core voltage override which is applied to the entire range of cpu core frequencies.
|
|
Valid Range 0 to 2000
|
|
**/
|
|
UINT16 CoreVoltageOverride;
|
|
|
|
/** Offset 0x0216 - Core Turbo voltage Adaptive
|
|
Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
|
|
Valid Range 0 to 2000
|
|
**/
|
|
UINT16 CoreVoltageAdaptive;
|
|
|
|
/** Offset 0x0218 - Core Turbo voltage Offset
|
|
The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
|
|
**/
|
|
UINT16 CoreVoltageOffset;
|
|
|
|
/** Offset 0x021A - Ring Downbin
|
|
Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
|
|
lower than the core ratio.<b>0: Disable</b>; 1: Enable.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RingDownBin;
|
|
|
|
/** Offset 0x021B - Ring voltage mode
|
|
Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RingVoltageMode;
|
|
|
|
/** Offset 0x021C - Ring voltage override
|
|
The ring voltage override which is applied to the entire range of cpu ring frequencies.
|
|
Valid Range 0 to 2000
|
|
**/
|
|
UINT16 RingVoltageOverride;
|
|
|
|
/** Offset 0x021E - Ring Turbo voltage Adaptive
|
|
Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
|
|
Valid Range 0 to 2000
|
|
**/
|
|
UINT16 RingVoltageAdaptive;
|
|
|
|
/** Offset 0x0220 - Ring Turbo voltage Offset
|
|
The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
|
|
**/
|
|
UINT16 RingVoltageOffset;
|
|
|
|
/** Offset 0x0222 - TjMax Offset
|
|
TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
|
|
TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
|
|
**/
|
|
UINT8 TjMaxOffset;
|
|
|
|
/** Offset 0x0223 - BiosGuard
|
|
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 BiosGuard;
|
|
|
|
/** Offset 0x0224
|
|
**/
|
|
UINT8 BiosGuardToolsInterface;
|
|
|
|
/** Offset 0x0225 - EnableSgx
|
|
Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
|
|
0: Disable, 1: Enable, 2: Software Control
|
|
**/
|
|
UINT8 EnableSgx;
|
|
|
|
/** Offset 0x0226 - Txt
|
|
Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 Txt;
|
|
|
|
/** Offset 0x0227
|
|
**/
|
|
UINT8 UnusedUpdSpace6;
|
|
|
|
/** Offset 0x0228 - PrmrrSize
|
|
0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000
|
|
**/
|
|
UINT32 PrmrrSize;
|
|
|
|
/** Offset 0x022C - SinitMemorySize
|
|
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
|
|
**/
|
|
UINT32 SinitMemorySize;
|
|
|
|
/** Offset 0x0230 - TxtHeapMemorySize
|
|
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
|
|
**/
|
|
UINT32 TxtHeapMemorySize;
|
|
|
|
/** Offset 0x0234 - TxtDprMemorySize
|
|
Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
|
|
**/
|
|
UINT32 TxtDprMemorySize;
|
|
|
|
/** Offset 0x0238 - TxtDprMemoryBase
|
|
Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
|
|
**/
|
|
UINT64 TxtDprMemoryBase;
|
|
|
|
/** Offset 0x0240 - BiosAcmBase
|
|
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
|
|
**/
|
|
UINT32 BiosAcmBase;
|
|
|
|
/** Offset 0x0244 - BiosAcmSize
|
|
Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
|
|
**/
|
|
UINT32 BiosAcmSize;
|
|
|
|
/** Offset 0x0248 - ApStartupBase
|
|
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
|
|
**/
|
|
UINT32 ApStartupBase;
|
|
|
|
/** Offset 0x024C - TgaSize
|
|
Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
|
|
**/
|
|
UINT32 TgaSize;
|
|
|
|
/** Offset 0x0250 - TxtLcpPdBase
|
|
Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
|
|
**/
|
|
UINT64 TxtLcpPdBase;
|
|
|
|
/** Offset 0x0258 - TxtLcpPdSize
|
|
Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
|
|
**/
|
|
UINT64 TxtLcpPdSize;
|
|
|
|
/** Offset 0x0260 - IsTPMPresence
|
|
IsTPMPresence default values
|
|
**/
|
|
UINT8 IsTPMPresence;
|
|
|
|
/** Offset 0x0261 - ReservedSecurityPreMem
|
|
Reserved for Security Pre-Mem
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ReservedSecurityPreMem[15];
|
|
|
|
/** Offset 0x0270 - Enable PCH HSIO PCIE Rx Set Ctle
|
|
Enable PCH PCIe Gen 3 Set CTLE Value.
|
|
**/
|
|
UINT8 PchPcieHsioRxSetCtleEnable[24];
|
|
|
|
/** Offset 0x0288 - PCH HSIO PCIE Rx Set Ctle Value
|
|
PCH PCIe Gen 3 Set CTLE Value.
|
|
**/
|
|
UINT8 PchPcieHsioRxSetCtle[24];
|
|
|
|
/** Offset 0x02A0 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];
|
|
|
|
/** Offset 0x02B8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
|
|
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen1DownscaleAmp[24];
|
|
|
|
/** Offset 0x02D0 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];
|
|
|
|
/** Offset 0x02E8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
|
|
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen2DownscaleAmp[24];
|
|
|
|
/** Offset 0x0300 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];
|
|
|
|
/** Offset 0x0318 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
|
|
PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen3DownscaleAmp[24];
|
|
|
|
/** Offset 0x0330 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen1DeEmphEnable[24];
|
|
|
|
/** Offset 0x0348 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
|
|
PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen1DeEmph[24];
|
|
|
|
/** Offset 0x0360 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];
|
|
|
|
/** Offset 0x0378 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
|
|
PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen2DeEmph3p5[24];
|
|
|
|
/** Offset 0x0390 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];
|
|
|
|
/** Offset 0x03A8 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
|
|
PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
|
|
**/
|
|
UINT8 PchPcieHsioTxGen2DeEmph6p0[24];
|
|
|
|
/** Offset 0x03C0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
|
|
|
|
/** Offset 0x03C8 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
|
|
PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
|
|
**/
|
|
UINT8 PchSataHsioRxGen1EqBoostMag[8];
|
|
|
|
/** Offset 0x03D0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
|
|
|
|
/** Offset 0x03D8 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
|
|
PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
|
|
**/
|
|
UINT8 PchSataHsioRxGen2EqBoostMag[8];
|
|
|
|
/** Offset 0x03E0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
|
|
|
|
/** Offset 0x03E8 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
|
|
PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
|
|
**/
|
|
UINT8 PchSataHsioRxGen3EqBoostMag[8];
|
|
|
|
/** Offset 0x03F0 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
|
|
|
|
/** Offset 0x03F8 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
|
|
PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
|
|
**/
|
|
UINT8 PchSataHsioTxGen1DownscaleAmp[8];
|
|
|
|
/** Offset 0x0400 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
|
|
|
|
/** Offset 0x0408 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
|
|
PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
|
|
**/
|
|
UINT8 PchSataHsioTxGen2DownscaleAmp[8];
|
|
|
|
/** Offset 0x0410 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
|
|
|
|
/** Offset 0x0418 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
|
|
PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
|
|
**/
|
|
UINT8 PchSataHsioTxGen3DownscaleAmp[8];
|
|
|
|
/** Offset 0x0420 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchSataHsioTxGen1DeEmphEnable[8];
|
|
|
|
/** Offset 0x0428 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
|
|
PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
|
|
**/
|
|
UINT8 PchSataHsioTxGen1DeEmph[8];
|
|
|
|
/** Offset 0x0430 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchSataHsioTxGen2DeEmphEnable[8];
|
|
|
|
/** Offset 0x0438 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
|
|
PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
|
|
**/
|
|
UINT8 PchSataHsioTxGen2DeEmph[8];
|
|
|
|
/** Offset 0x0440 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
|
|
0: Disable; 1: Enable.
|
|
**/
|
|
UINT8 PchSataHsioTxGen3DeEmphEnable[8];
|
|
|
|
/** Offset 0x0448 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
|
|
PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
|
|
**/
|
|
UINT8 PchSataHsioTxGen3DeEmph[8];
|
|
|
|
/** Offset 0x0450 - PCH LPC Enhance the port 8xh decoding
|
|
Original LPC only decodes one byte of port 80h.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PchLpcEnhancePort8xhDecoding;
|
|
|
|
/** Offset 0x0451 - PCH Port80 Route
|
|
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PchPort80Route;
|
|
|
|
/** Offset 0x0452 - Enable SMBus ARP support
|
|
Enable SMBus ARP support.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SmbusArpEnable;
|
|
|
|
/** Offset 0x0453 - Number of RsvdSmbusAddressTable.
|
|
The number of elements in the RsvdSmbusAddressTable.
|
|
**/
|
|
UINT8 PchNumRsvdSmbusAddresses;
|
|
|
|
/** Offset 0x0454 - SMBUS Base Address
|
|
SMBUS Base Address (IO space).
|
|
**/
|
|
UINT16 PchSmbusIoBase;
|
|
|
|
/** Offset 0x0456 - Size of PCIe IMR.
|
|
Size of PCIe IMR in megabytes
|
|
**/
|
|
UINT16 PcieImrSize;
|
|
|
|
/** Offset 0x0458 - Point of RsvdSmbusAddressTable
|
|
Array of addresses reserved for non-ARP-capable SMBus devices.
|
|
**/
|
|
UINT32 RsvdSmbusAddressTablePtr;
|
|
|
|
/** Offset 0x045C - Enable PCIE RP Mask
|
|
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
|
|
for port1, bit1 for port2, and so on.
|
|
**/
|
|
UINT32 PcieRpEnableMask;
|
|
|
|
/** Offset 0x0460 - Enable PCIe IMR
|
|
0:Disable, 1:Enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PcieImrEnabled;
|
|
|
|
/** Offset 0x0461 - Root port number for IMR.
|
|
Root port number for IMR.
|
|
**/
|
|
UINT8 ImrRpSelection;
|
|
|
|
/** Offset 0x0462 - Enable SMBus Alert Pin
|
|
Enable SMBus Alert Pin.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PchSmbAlertEnable;
|
|
|
|
/** Offset 0x0463 - ReservedSecurityPreMem
|
|
Reserved for Security Pre-Mem
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ReservedPchPreMem[13];
|
|
|
|
/** Offset 0x0470 - Debug Interfaces
|
|
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
|
|
BIT2 - Not used.
|
|
**/
|
|
UINT8 PcdDebugInterfaceFlags;
|
|
|
|
/** Offset 0x0471 - PcdSerialIoUartNumber
|
|
Select SerialIo Uart Controller for debug.
|
|
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
|
**/
|
|
UINT8 PcdSerialIoUartNumber;
|
|
|
|
/** Offset 0x0472 - ISA Serial Base selection
|
|
Select ISA Serial Base address. Default is 0x3F8.
|
|
0:0x3F8, 1:0x2F8
|
|
**/
|
|
UINT8 PcdIsaSerialUartBase;
|
|
|
|
/** Offset 0x0473 - GT PLL voltage offset
|
|
Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
|
|
**/
|
|
UINT8 GtPllVoltageOffset;
|
|
|
|
/** Offset 0x0474 - Ring PLL voltage offset
|
|
Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
|
|
**/
|
|
UINT8 RingPllVoltageOffset;
|
|
|
|
/** Offset 0x0475 - System Agent PLL voltage offset
|
|
Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
|
|
**/
|
|
UINT8 SaPllVoltageOffset;
|
|
|
|
/** Offset 0x0476 - Memory Controller PLL voltage offset
|
|
Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
|
|
**/
|
|
UINT8 McPllVoltageOffset;
|
|
|
|
/** Offset 0x0477 - MRC Safe Config
|
|
Enables/Disable MRC Safe Config
|
|
$EN_DIS
|
|
**/
|
|
UINT8 MrcSafeConfig;
|
|
|
|
/** Offset 0x0478 - PcdSerialDebugBaudRate
|
|
Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
|
|
3:9600, 4:19200, 6:56700, 7:115200
|
|
**/
|
|
UINT8 PcdSerialDebugBaudRate;
|
|
|
|
/** Offset 0x0479 - HobBufferSize
|
|
Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
|
|
total HOB size).
|
|
0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
|
|
**/
|
|
UINT8 HobBufferSize;
|
|
|
|
/** Offset 0x047A - Early Command Training
|
|
Enables/Disable Early Command Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ECT;
|
|
|
|
/** Offset 0x047B - SenseAmp Offset Training
|
|
Enables/Disable SenseAmp Offset Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SOT;
|
|
|
|
/** Offset 0x047C - Early ReadMPR Timing Centering 2D
|
|
Enables/Disable Early ReadMPR Timing Centering 2D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ERDMPRTC2D;
|
|
|
|
/** Offset 0x047D - Read MPR Training
|
|
Enables/Disable Read MPR Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RDMPRT;
|
|
|
|
/** Offset 0x047E - Receive Enable Training
|
|
Enables/Disable Receive Enable Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RCVET;
|
|
|
|
/** Offset 0x047F - Jedec Write Leveling
|
|
Enables/Disable Jedec Write Leveling
|
|
$EN_DIS
|
|
**/
|
|
UINT8 JWRL;
|
|
|
|
/** Offset 0x0480 - Early Write Time Centering 2D
|
|
Enables/Disable Early Write Time Centering 2D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EWRTC2D;
|
|
|
|
/** Offset 0x0481 - Early Read Time Centering 2D
|
|
Enables/Disable Early Read Time Centering 2D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ERDTC2D;
|
|
|
|
/** Offset 0x0482 - Write Timing Centering 1D
|
|
Enables/Disable Write Timing Centering 1D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 WRTC1D;
|
|
|
|
/** Offset 0x0483 - Write Voltage Centering 1D
|
|
Enables/Disable Write Voltage Centering 1D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 WRVC1D;
|
|
|
|
/** Offset 0x0484 - Read Timing Centering 1D
|
|
Enables/Disable Read Timing Centering 1D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RDTC1D;
|
|
|
|
/** Offset 0x0485 - Dimm ODT Training
|
|
Enables/Disable Dimm ODT Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 DIMMODTT;
|
|
|
|
/** Offset 0x0486 - DIMM RON Training
|
|
Enables/Disable DIMM RON Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 DIMMRONT;
|
|
|
|
/** Offset 0x0487 - Write Drive Strength/Equalization 2D
|
|
Enables/Disable Write Drive Strength/Equalization 2D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 WRDSEQT;
|
|
|
|
/** Offset 0x0488 - Write Slew Rate Training
|
|
Enables/Disable Write Slew Rate Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 WRSRT;
|
|
|
|
/** Offset 0x0489 - Read ODT Training
|
|
Enables/Disable Read ODT Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RDODTT;
|
|
|
|
/** Offset 0x048A - Read Equalization Training
|
|
Enables/Disable Read Equalization Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RDEQT;
|
|
|
|
/** Offset 0x048B - Read Amplifier Training
|
|
Enables/Disable Read Amplifier Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RDAPT;
|
|
|
|
/** Offset 0x048C - Write Timing Centering 2D
|
|
Enables/Disable Write Timing Centering 2D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 WRTC2D;
|
|
|
|
/** Offset 0x048D - Read Timing Centering 2D
|
|
Enables/Disable Read Timing Centering 2D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RDTC2D;
|
|
|
|
/** Offset 0x048E - Write Voltage Centering 2D
|
|
Enables/Disable Write Voltage Centering 2D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 WRVC2D;
|
|
|
|
/** Offset 0x048F - Read Voltage Centering 2D
|
|
Enables/Disable Read Voltage Centering 2D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RDVC2D;
|
|
|
|
/** Offset 0x0490 - Command Voltage Centering
|
|
Enables/Disable Command Voltage Centering
|
|
$EN_DIS
|
|
**/
|
|
UINT8 CMDVC;
|
|
|
|
/** Offset 0x0491 - Late Command Training
|
|
Enables/Disable Late Command Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 LCT;
|
|
|
|
/** Offset 0x0492 - Round Trip Latency Training
|
|
Enables/Disable Round Trip Latency Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RTL;
|
|
|
|
/** Offset 0x0493 - Turn Around Timing Training
|
|
Enables/Disable Turn Around Timing Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 TAT;
|
|
|
|
/** Offset 0x0494 - Memory Test
|
|
Enables/Disable Memory Test
|
|
$EN_DIS
|
|
**/
|
|
UINT8 MEMTST;
|
|
|
|
/** Offset 0x0495 - DIMM SPD Alias Test
|
|
Enables/Disable DIMM SPD Alias Test
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ALIASCHK;
|
|
|
|
/** Offset 0x0496 - Receive Enable Centering 1D
|
|
Enables/Disable Receive Enable Centering 1D
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RCVENC1D;
|
|
|
|
/** Offset 0x0497 - Retrain Margin Check
|
|
Enables/Disable Retrain Margin Check
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RMC;
|
|
|
|
/** Offset 0x0498 - Write Drive Strength Up/Dn independently
|
|
Enables/Disable Write Drive Strength Up/Dn independently
|
|
$EN_DIS
|
|
**/
|
|
UINT8 WRDSUDT;
|
|
|
|
/** Offset 0x0499 - ECC Support
|
|
Enables/Disable ECC Support
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EccSupport;
|
|
|
|
/** Offset 0x049A - Memory Remap
|
|
Enables/Disable Memory Remap
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RemapEnable;
|
|
|
|
/** Offset 0x049B - Rank Interleave support
|
|
Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
|
|
the same time.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RankInterleave;
|
|
|
|
/** Offset 0x049C - Enhanced Interleave support
|
|
Enables/Disable Enhanced Interleave support
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EnhancedInterleave;
|
|
|
|
/** Offset 0x049D - Memory Trace
|
|
Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of
|
|
equal size. This option may change TOLUD and REMAP values as needed.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 MemoryTrace;
|
|
|
|
/** Offset 0x049E - Ch Hash Support
|
|
Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ChHashEnable;
|
|
|
|
/** Offset 0x049F - Extern Therm Status
|
|
Enables/Disable Extern Therm Status
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EnableExtts;
|
|
|
|
/** Offset 0x04A0 - Closed Loop Therm Manage
|
|
Enables/Disable Closed Loop Therm Manage
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EnableCltm;
|
|
|
|
/** Offset 0x04A1 - Open Loop Therm Manage
|
|
Enables/Disable Open Loop Therm Manage
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EnableOltm;
|
|
|
|
/** Offset 0x04A2 - DDR PowerDown and idle counter
|
|
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EnablePwrDn;
|
|
|
|
/** Offset 0x04A3 - DDR PowerDown and idle counter
|
|
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EnablePwrDnLpddr;
|
|
|
|
/** Offset 0x04A4 - Use user provided power weights, scale factor, and channel power floor values
|
|
Enables/Disable Use user provided power weights, scale factor, and channel power
|
|
floor values
|
|
$EN_DIS
|
|
**/
|
|
UINT8 UserPowerWeightsEn;
|
|
|
|
/** Offset 0x04A5 - RAPL PL Lock
|
|
Enables/Disable RAPL PL Lock
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RaplLim2Lock;
|
|
|
|
/** Offset 0x04A6 - RAPL PL 2 enable
|
|
Enables/Disable RAPL PL 2 enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RaplLim2Ena;
|
|
|
|
/** Offset 0x04A7 - RAPL PL 1 enable
|
|
Enables/Disable RAPL PL 1 enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RaplLim1Ena;
|
|
|
|
/** Offset 0x04A8 - SelfRefresh Enable
|
|
Enables/Disable SelfRefresh Enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SrefCfgEna;
|
|
|
|
/** Offset 0x04A9 - Throttler CKEMin Defeature
|
|
Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ThrtCkeMinDefeatLpddr;
|
|
|
|
/** Offset 0x04AA - Throttler CKEMin Defeature
|
|
Enables/Disable Throttler CKEMin Defeature
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ThrtCkeMinDefeat;
|
|
|
|
/** Offset 0x04AB - Enable RH Prevention
|
|
Enables/Disable RH Prevention
|
|
$EN_DIS
|
|
**/
|
|
UINT8 RhPrevention;
|
|
|
|
/** Offset 0x04AC - Exit On Failure (MRC)
|
|
Enables/Disable Exit On Failure (MRC)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ExitOnFailure;
|
|
|
|
/** Offset 0x04AD - LPDDR Thermal Sensor
|
|
Enables/Disable LPDDR Thermal Sensor
|
|
$EN_DIS
|
|
**/
|
|
UINT8 DdrThermalSensor;
|
|
|
|
/** Offset 0x04AE - EV Loader
|
|
Enable/Disable EV Loader Functionality
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EvLoader;
|
|
|
|
/** Offset 0x04AF - EV Loader Delay
|
|
Enable/Disable EV Loader 2 Second Delay
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EvLoaderDelay;
|
|
|
|
/** Offset 0x04B0 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
|
|
Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
|
|
$EN_DIS
|
|
**/
|
|
UINT8 Ddr4DdpSharedClock;
|
|
|
|
/** Offset 0x04B1 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
|
|
ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
|
|
$EN_DIS
|
|
**/
|
|
UINT8 Ddr4DdpSharedZq;
|
|
|
|
/** Offset 0x04B2 - Ch Hash Mask
|
|
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
|
|
BITS [19:6
|
|
**/
|
|
UINT16 ChHashMask;
|
|
|
|
/** Offset 0x04B4 - Base reference clock value
|
|
Base reference clock value, in Hertz(Default is 125Hz)
|
|
100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
|
|
**/
|
|
UINT32 BClkFrequency;
|
|
|
|
/** Offset 0x04B8 - Ch Hash Interleaved Bit
|
|
Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
|
|
the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
|
|
0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
|
|
**/
|
|
UINT8 ChHashInterleaveBit;
|
|
|
|
/** Offset 0x04B9 - Energy Scale Factor
|
|
Energy Scale Factor, Default is 4
|
|
**/
|
|
UINT8 EnergyScaleFact;
|
|
|
|
/** Offset 0x04BA - EPG DIMM Idd3N
|
|
Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
|
|
a per DIMM basis. Default is 26
|
|
**/
|
|
UINT16 Idd3n;
|
|
|
|
/** Offset 0x04BC - EPG DIMM Idd3P
|
|
Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
|
|
on a per DIMM basis. Default is 11
|
|
**/
|
|
UINT16 Idd3p;
|
|
|
|
/** Offset 0x04BE - CMD Slew Rate Training
|
|
Enable/Disable CMD Slew Rate Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 CMDSR;
|
|
|
|
/** Offset 0x04BF - CMD Drive Strength and Tx Equalization
|
|
Enable/Disable CMD Drive Strength and Tx Equalization
|
|
$EN_DIS
|
|
**/
|
|
UINT8 CMDDSEQ;
|
|
|
|
/** Offset 0x04C0 - CMD Normalization
|
|
Enable/Disable CMD Normalization
|
|
$EN_DIS
|
|
**/
|
|
UINT8 CMDNORM;
|
|
|
|
/** Offset 0x04C1 - Early DQ Write Drive Strength and Equalization Training
|
|
Enable/Disable Early DQ Write Drive Strength and Equalization Training
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EWRDSEQ;
|
|
|
|
/** Offset 0x04C2 - RH Activation Probability
|
|
RH Activation Probability, Probability value is 1/2^(inputvalue)
|
|
**/
|
|
UINT8 RhActProbability;
|
|
|
|
/** Offset 0x04C3 - RAPL PL 2 WindowX
|
|
Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
|
|
**/
|
|
UINT8 RaplLim2WindX;
|
|
|
|
/** Offset 0x04C4 - RAPL PL 2 WindowY
|
|
Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
|
|
**/
|
|
UINT8 RaplLim2WindY;
|
|
|
|
/** Offset 0x04C5 - RAPL PL 1 WindowX
|
|
Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
|
|
**/
|
|
UINT8 RaplLim1WindX;
|
|
|
|
/** Offset 0x04C6 - RAPL PL 1 WindowY
|
|
Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
|
|
**/
|
|
UINT8 RaplLim1WindY;
|
|
|
|
/** Offset 0x04C7
|
|
**/
|
|
UINT8 UnusedUpdSpace7;
|
|
|
|
/** Offset 0x04C8 - RAPL PL 2 Power
|
|
range[0;2^14-1]= [2047.875;0]in W, (224= Def)
|
|
**/
|
|
UINT16 RaplLim2Pwr;
|
|
|
|
/** Offset 0x04CA - RAPL PL 1 Power
|
|
range[0;2^14-1]= [2047.875;0]in W, (224= Def)
|
|
**/
|
|
UINT16 RaplLim1Pwr;
|
|
|
|
/** Offset 0x04CC - Warm Threshold Ch0 Dimm0
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
|
|
**/
|
|
UINT8 WarmThresholdCh0Dimm0;
|
|
|
|
/** Offset 0x04CD - Warm Threshold Ch0 Dimm1
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
|
|
**/
|
|
UINT8 WarmThresholdCh0Dimm1;
|
|
|
|
/** Offset 0x04CE - Warm Threshold Ch1 Dimm0
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
|
|
**/
|
|
UINT8 WarmThresholdCh1Dimm0;
|
|
|
|
/** Offset 0x04CF - Warm Threshold Ch1 Dimm1
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
|
|
**/
|
|
UINT8 WarmThresholdCh1Dimm1;
|
|
|
|
/** Offset 0x04D0 - Hot Threshold Ch0 Dimm0
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
|
|
**/
|
|
UINT8 HotThresholdCh0Dimm0;
|
|
|
|
/** Offset 0x04D1 - Hot Threshold Ch0 Dimm1
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
|
|
**/
|
|
UINT8 HotThresholdCh0Dimm1;
|
|
|
|
/** Offset 0x04D2 - Hot Threshold Ch1 Dimm0
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
|
|
**/
|
|
UINT8 HotThresholdCh1Dimm0;
|
|
|
|
/** Offset 0x04D3 - Hot Threshold Ch1 Dimm1
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
|
|
**/
|
|
UINT8 HotThresholdCh1Dimm1;
|
|
|
|
/** Offset 0x04D4 - Warm Budget Ch0 Dimm0
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
|
|
**/
|
|
UINT8 WarmBudgetCh0Dimm0;
|
|
|
|
/** Offset 0x04D5 - Warm Budget Ch0 Dimm1
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
|
|
**/
|
|
UINT8 WarmBudgetCh0Dimm1;
|
|
|
|
/** Offset 0x04D6 - Warm Budget Ch1 Dimm0
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
|
|
**/
|
|
UINT8 WarmBudgetCh1Dimm0;
|
|
|
|
/** Offset 0x04D7 - Warm Budget Ch1 Dimm1
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
|
|
**/
|
|
UINT8 WarmBudgetCh1Dimm1;
|
|
|
|
/** Offset 0x04D8 - Hot Budget Ch0 Dimm0
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
|
|
**/
|
|
UINT8 HotBudgetCh0Dimm0;
|
|
|
|
/** Offset 0x04D9 - Hot Budget Ch0 Dimm1
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
|
|
**/
|
|
UINT8 HotBudgetCh0Dimm1;
|
|
|
|
/** Offset 0x04DA - Hot Budget Ch1 Dimm0
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
|
|
**/
|
|
UINT8 HotBudgetCh1Dimm0;
|
|
|
|
/** Offset 0x04DB - Hot Budget Ch1 Dimm1
|
|
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
|
|
**/
|
|
UINT8 HotBudgetCh1Dimm1;
|
|
|
|
/** Offset 0x04DC - Idle Energy Ch0Dimm0
|
|
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
|
|
**/
|
|
UINT8 IdleEnergyCh0Dimm0;
|
|
|
|
/** Offset 0x04DD - Idle Energy Ch0Dimm1
|
|
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
|
|
**/
|
|
UINT8 IdleEnergyCh0Dimm1;
|
|
|
|
/** Offset 0x04DE - Idle Energy Ch1Dimm0
|
|
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
|
|
**/
|
|
UINT8 IdleEnergyCh1Dimm0;
|
|
|
|
/** Offset 0x04DF - Idle Energy Ch1Dimm1
|
|
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
|
|
**/
|
|
UINT8 IdleEnergyCh1Dimm1;
|
|
|
|
/** Offset 0x04E0 - PowerDown Energy Ch0Dimm0
|
|
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
|
|
**/
|
|
UINT8 PdEnergyCh0Dimm0;
|
|
|
|
/** Offset 0x04E1 - PowerDown Energy Ch0Dimm1
|
|
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
|
|
**/
|
|
UINT8 PdEnergyCh0Dimm1;
|
|
|
|
/** Offset 0x04E2 - PowerDown Energy Ch1Dimm0
|
|
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
|
|
**/
|
|
UINT8 PdEnergyCh1Dimm0;
|
|
|
|
/** Offset 0x04E3 - PowerDown Energy Ch1Dimm1
|
|
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
|
|
**/
|
|
UINT8 PdEnergyCh1Dimm1;
|
|
|
|
/** Offset 0x04E4 - Activate Energy Ch0Dimm0
|
|
Activate Energy Contribution, range[255;0],(172= Def)
|
|
**/
|
|
UINT8 ActEnergyCh0Dimm0;
|
|
|
|
/** Offset 0x04E5 - Activate Energy Ch0Dimm1
|
|
Activate Energy Contribution, range[255;0],(172= Def)
|
|
**/
|
|
UINT8 ActEnergyCh0Dimm1;
|
|
|
|
/** Offset 0x04E6 - Activate Energy Ch1Dimm0
|
|
Activate Energy Contribution, range[255;0],(172= Def)
|
|
**/
|
|
UINT8 ActEnergyCh1Dimm0;
|
|
|
|
/** Offset 0x04E7 - Activate Energy Ch1Dimm1
|
|
Activate Energy Contribution, range[255;0],(172= Def)
|
|
**/
|
|
UINT8 ActEnergyCh1Dimm1;
|
|
|
|
/** Offset 0x04E8 - Read Energy Ch0Dimm0
|
|
Read Energy Contribution, range[255;0],(212= Def)
|
|
**/
|
|
UINT8 RdEnergyCh0Dimm0;
|
|
|
|
/** Offset 0x04E9 - Read Energy Ch0Dimm1
|
|
Read Energy Contribution, range[255;0],(212= Def)
|
|
**/
|
|
UINT8 RdEnergyCh0Dimm1;
|
|
|
|
/** Offset 0x04EA - Read Energy Ch1Dimm0
|
|
Read Energy Contribution, range[255;0],(212= Def)
|
|
**/
|
|
UINT8 RdEnergyCh1Dimm0;
|
|
|
|
/** Offset 0x04EB - Read Energy Ch1Dimm1
|
|
Read Energy Contribution, range[255;0],(212= Def)
|
|
**/
|
|
UINT8 RdEnergyCh1Dimm1;
|
|
|
|
/** Offset 0x04EC - Write Energy Ch0Dimm0
|
|
Write Energy Contribution, range[255;0],(221= Def)
|
|
**/
|
|
UINT8 WrEnergyCh0Dimm0;
|
|
|
|
/** Offset 0x04ED - Write Energy Ch0Dimm1
|
|
Write Energy Contribution, range[255;0],(221= Def)
|
|
**/
|
|
UINT8 WrEnergyCh0Dimm1;
|
|
|
|
/** Offset 0x04EE - Write Energy Ch1Dimm0
|
|
Write Energy Contribution, range[255;0],(221= Def)
|
|
**/
|
|
UINT8 WrEnergyCh1Dimm0;
|
|
|
|
/** Offset 0x04EF - Write Energy Ch1Dimm1
|
|
Write Energy Contribution, range[255;0],(221= Def)
|
|
**/
|
|
UINT8 WrEnergyCh1Dimm1;
|
|
|
|
/** Offset 0x04F0 - Throttler CKEMin Timer
|
|
Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
|
|
Dfault is 0x30
|
|
**/
|
|
UINT8 ThrtCkeMinTmr;
|
|
|
|
/** Offset 0x04F1 - Cke Rank Mapping
|
|
Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies
|
|
which rank CKE[i] goes to.
|
|
**/
|
|
UINT8 CkeRankMapping;
|
|
|
|
/** Offset 0x04F2 - Rapl Power Floor Ch0
|
|
Power budget ,range[255;0],(0= 5.3W Def)
|
|
**/
|
|
UINT8 RaplPwrFlCh0;
|
|
|
|
/** Offset 0x04F3 - Rapl Power Floor Ch1
|
|
Power budget ,range[255;0],(0= 5.3W Def)
|
|
**/
|
|
UINT8 RaplPwrFlCh1;
|
|
|
|
/** Offset 0x04F4 - Command Rate Support
|
|
CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
|
|
0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS
|
|
**/
|
|
UINT8 EnCmdRate;
|
|
|
|
/** Offset 0x04F5 - REFRESH_2X_MODE
|
|
0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
|
|
0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
|
|
**/
|
|
UINT8 Refresh2X;
|
|
|
|
/** Offset 0x04F6 - Energy Performance Gain
|
|
Enable/disable(default) Energy Performance Gain.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 EpgEnable;
|
|
|
|
/** Offset 0x04F7 - Row Hammer Solution
|
|
Type of method used to prevent Row Hammer. Default is Hardware RHP
|
|
0:Hardware RHP, 1:2x Refresh
|
|
**/
|
|
UINT8 RhSolution;
|
|
|
|
/** Offset 0x04F8 - User Manual Threshold
|
|
Disabled: Predefined threshold will be used.\n
|
|
Enabled: User Input will be used.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 UserThresholdEnable;
|
|
|
|
/** Offset 0x04F9 - User Manual Budget
|
|
Disabled: Configuration of memories will defined the Budget value.\n
|
|
Enabled: User Input will be used.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 UserBudgetEnable;
|
|
|
|
/** Offset 0x04FA - TcritMax
|
|
Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax
|
|
has to be greater than THIGHMax .\n
|
|
Critical temperature will be TcritMax
|
|
**/
|
|
UINT8 TsodTcritMax;
|
|
|
|
/** Offset 0x04FB - Event mode
|
|
Disable:Comparator mode.\n
|
|
Enable:Interrupt mode
|
|
$EN_DIS
|
|
**/
|
|
UINT8 TsodEventMode;
|
|
|
|
/** Offset 0x04FC - EVENT polarity
|
|
Disable:Active LOW.\n
|
|
Enable:Active HIGH
|
|
$EN_DIS
|
|
**/
|
|
UINT8 TsodEventPolarity;
|
|
|
|
/** Offset 0x04FD - Critical event only
|
|
Disable:Trips on alarm or critical.\n
|
|
Enable:Trips only if criticaal temperature is reached
|
|
$EN_DIS
|
|
**/
|
|
UINT8 TsodCriticalEventOnly;
|
|
|
|
/** Offset 0x04FE - Event output control
|
|
Disable:Event output disable.\n
|
|
Enable:Event output enabled
|
|
$EN_DIS
|
|
**/
|
|
UINT8 TsodEventOutputControl;
|
|
|
|
/** Offset 0x04FF - Alarm window lock bit
|
|
Disable:Alarm trips are not locked and can be changed.\n
|
|
Enable:Alarm trips are locked and cannot be changed
|
|
$EN_DIS
|
|
**/
|
|
UINT8 TsodAlarmwindowLockBit;
|
|
|
|
/** Offset 0x0500 - Critical trip lock bit
|
|
Disable:Critical trip is not locked and can be changed.\n
|
|
Enable:Critical trip is locked and cannot be changed
|
|
$EN_DIS
|
|
**/
|
|
UINT8 TsodCriticaltripLockBit;
|
|
|
|
/** Offset 0x0501 - Shutdown mode
|
|
Disable:Temperature sensor enable.\n
|
|
Enable:Temperature sensor disable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 TsodShutdownMode;
|
|
|
|
/** Offset 0x0502 - ThighMax
|
|
Thigh = ThighMax (Default is 93)
|
|
**/
|
|
UINT8 TsodThigMax;
|
|
|
|
/** Offset 0x0503 - User Manual Thig and Tcrit
|
|
Disabled(Default): Temperature will be given by the configuration of memories and
|
|
1x or 2xrefresh rate.\n
|
|
Enabled: User Input will define for Thigh and Tcrit.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 TsodManualEnable;
|
|
|
|
/** Offset 0x0504 - Force OLTM or 2X Refresh when needed
|
|
Disabled(Default): = Force OLTM.\n
|
|
Enabled: = Force 2x Refresh.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ForceOltmOrRefresh2x;
|
|
|
|
/** Offset 0x0505 - Pwr Down Idle Timer
|
|
The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
|
|
AUTO: 64 for ULX/ULT, 128 for DT/Halo
|
|
**/
|
|
UINT8 PwdwnIdleCounter;
|
|
|
|
/** Offset 0x0506 - Bitmask of ranks that have CA bus terminated
|
|
Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
|
|
Rank0 is terminating and Rank1 is non-terminating</b>
|
|
**/
|
|
UINT8 CmdRanksTerminated;
|
|
|
|
/** Offset 0x0507 - GDXC MOT enable
|
|
GDXC MOT enable.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 GdxcEnable;
|
|
|
|
/** Offset 0x0508 - PcdSerialDebugLevel
|
|
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
|
|
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
|
|
Info & Verbose.
|
|
0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
|
|
Error Warnings and Info, 5:Load Error Warnings Info and Verbose
|
|
**/
|
|
UINT8 PcdSerialDebugLevel;
|
|
|
|
/** Offset 0x0509 - Fivr Faults
|
|
Fivr Faults; 0: Disabled; <b>1: Enabled.</b>
|
|
$EN_DIS
|
|
**/
|
|
UINT8 FivrFaults;
|
|
|
|
/** Offset 0x050A - Fivr Efficiency
|
|
Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b>
|
|
$EN_DIS
|
|
**/
|
|
UINT8 FivrEfficiency;
|
|
|
|
/** Offset 0x050B - Safe Mode Support
|
|
This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SafeMode;
|
|
|
|
/** Offset 0x050C - Ask MRC to clear memory content
|
|
Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 CleanMemory;
|
|
|
|
/** Offset 0x050D - LpDdrDqDqsReTraining
|
|
Enables/Disable LpDdrDqDqsReTraining
|
|
$EN_DIS
|
|
**/
|
|
UINT8 LpDdrDqDqsReTraining;
|
|
|
|
/** Offset 0x050E - Post Code Output Port
|
|
This option configures Post Code Output Port
|
|
**/
|
|
UINT16 PostCodeOutputPort;
|
|
|
|
/** Offset 0x0510 - RMTLoopCount
|
|
Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
|
|
**/
|
|
UINT8 RMTLoopCount;
|
|
|
|
/** Offset 0x0511
|
|
**/
|
|
UINT8 ReservedFspmUpd[15];
|
|
} FSP_M_CONFIG;
|
|
|
|
/** Fsp M Test Configuration
|
|
**/
|
|
typedef struct {
|
|
|
|
/** Offset 0x0520
|
|
**/
|
|
UINT32 Signature;
|
|
|
|
/** Offset 0x0524 - Skip external display device scanning
|
|
Enable: Do not scan for external display device, Disable (Default): Scan external
|
|
display devices
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SkipExtGfxScan;
|
|
|
|
/** Offset 0x0525 - Generate BIOS Data ACPI Table
|
|
Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
|
|
$EN_DIS
|
|
**/
|
|
UINT8 BdatEnable;
|
|
|
|
/** Offset 0x0526 - Detect External Graphics device for LegacyOpROM
|
|
Detect and report if external graphics device only support LegacyOpROM or not (to
|
|
support CSM auto-enable). Enable(Default)=1, Disable=0
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ScanExtGfxForLegacyOpRom;
|
|
|
|
/** Offset 0x0527 - Lock PCU Thermal Management registers
|
|
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
|
|
$EN_DIS
|
|
**/
|
|
UINT8 LockPTMregs;
|
|
|
|
/** Offset 0x0528 - DMI Max Link Speed
|
|
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
|
|
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
|
|
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
|
|
**/
|
|
UINT8 DmiMaxLinkSpeed;
|
|
|
|
/** Offset 0x0529 - DMI Equalization Phase 2
|
|
DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
|
|
AUTO - Use the current default method
|
|
0:Disable phase2, 1:Enable phase2, 2:Auto
|
|
**/
|
|
UINT8 DmiGen3EqPh2Enable;
|
|
|
|
/** Offset 0x052A - DMI Gen3 Equalization Phase3
|
|
DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
|
|
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
|
|
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
|
|
EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
|
|
Phase1), Disabled(0x4): Bypass Equalization Phase 3
|
|
0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
|
|
**/
|
|
UINT8 DmiGen3EqPh3Method;
|
|
|
|
/** Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0.
|
|
Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
|
|
Enable phase 2, Auto(0x2)(Default): Use the current default method
|
|
0:Disable, 1:Enable, 2:Auto
|
|
**/
|
|
UINT8 Peg0Gen3EqPh2Enable;
|
|
|
|
/** Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1.
|
|
Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
|
|
Enable phase 2, Auto(0x2)(Default): Use the current default method
|
|
0:Disable, 1:Enable, 2:Auto
|
|
**/
|
|
UINT8 Peg1Gen3EqPh2Enable;
|
|
|
|
/** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2.
|
|
Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
|
|
Enable phase 2, Auto(0x2)(Default): Use the current default method
|
|
0:Disable, 1:Enable, 2:Auto
|
|
**/
|
|
UINT8 Peg2Gen3EqPh2Enable;
|
|
|
|
/** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3.
|
|
Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
|
|
Enable phase 2, Auto(0x2)(Default): Use the current default method
|
|
0:Disable, 1:Enable, 2:Auto
|
|
**/
|
|
UINT8 Peg3Gen3EqPh2Enable;
|
|
|
|
/** Offset 0x052F - Phase3 EQ method on the PEG 0:1:0.
|
|
PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
|
|
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
|
|
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
|
|
EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
|
|
Phase1), Disabled(0x4): Bypass Equalization Phase 3
|
|
0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
|
|
**/
|
|
UINT8 Peg0Gen3EqPh3Method;
|
|
|
|
/** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1.
|
|
PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
|
|
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
|
|
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
|
|
EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
|
|
Phase1), Disabled(0x4): Bypass Equalization Phase 3
|
|
0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
|
|
**/
|
|
UINT8 Peg1Gen3EqPh3Method;
|
|
|
|
/** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2.
|
|
PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
|
|
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
|
|
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
|
|
EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
|
|
Phase1), Disabled(0x4): Bypass Equalization Phase 3
|
|
0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
|
|
**/
|
|
UINT8 Peg2Gen3EqPh3Method;
|
|
|
|
/** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3.
|
|
PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
|
|
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
|
|
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
|
|
EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
|
|
Phase1), Disabled(0x4): Bypass Equalization Phase 3
|
|
0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
|
|
**/
|
|
UINT8 Peg3Gen3EqPh3Method;
|
|
|
|
/** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
|
|
Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
|
|
Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PegGen3ProgramStaticEq;
|
|
|
|
/** Offset 0x0534 - PEG Gen3 SwEq Always Attempt
|
|
Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default):
|
|
Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test
|
|
and generate new EQ values every boot, not recommended
|
|
0:Disable, 1:Enable
|
|
**/
|
|
UINT8 Gen3SwEqAlwaysAttempt;
|
|
|
|
/** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq
|
|
Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test
|
|
Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the
|
|
current default method (Default)Auto will test Presets 7, 3, and 5. It is possible
|
|
for this default to change over time;using Auto will ensure Reference Code always
|
|
uses the latest default settings
|
|
0:P7 P3 P5, 1:P0 to P9, 2:Auto
|
|
**/
|
|
UINT8 Gen3SwEqNumberOfPresets;
|
|
|
|
/** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq
|
|
Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization
|
|
Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default):
|
|
Use the current default
|
|
0:Disable, 1:Enable, 2:Auto
|
|
**/
|
|
UINT8 Gen3SwEqEnableVocTest;
|
|
|
|
/** Offset 0x0537 - PPCIe Rx Compliance Testing Mode
|
|
Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):
|
|
PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;
|
|
it should only be set when doing PCIe compliance testing
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PegRxCemTestingMode;
|
|
|
|
/** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled
|
|
the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0
|
|
**/
|
|
UINT8 PegRxCemLoopbackLane;
|
|
|
|
/** Offset 0x0539 - Generate PCIe BDAT Margin Table
|
|
Set this policy to enable the generation and addition of PCIe margin data to the
|
|
BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin
|
|
data generation, Enable(0x1): Generate PCIe BDAT margin data
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PegGenerateBdatMarginTable;
|
|
|
|
/** Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing
|
|
Set this policy to enable the generation and addition of PCIe margin data to the
|
|
BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness,
|
|
Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for
|
|
compliance testing
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PegRxCemNonProtocolAwareness;
|
|
|
|
/** Offset 0x053B - PCIe Override RxCTLE
|
|
Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
|
|
Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
|
|
peak values unmodified
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PegGen3RxCtleOverride;
|
|
|
|
/** Offset 0x053C - Rsvd
|
|
Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
|
|
Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
|
|
peak values unmodified
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PegGen3Rsvd;
|
|
|
|
/** Offset 0x053D - PEG Gen3 Root port preset values per lane
|
|
Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
|
|
**/
|
|
UINT8 PegGen3RootPortPreset[20];
|
|
|
|
/** Offset 0x0551 - PEG Gen3 End port preset values per lane
|
|
Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
|
|
**/
|
|
UINT8 PegGen3EndPointPreset[20];
|
|
|
|
/** Offset 0x0565 - PEG Gen3 End port Hint values per lane
|
|
Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
|
|
**/
|
|
UINT8 PegGen3EndPointHint[20];
|
|
|
|
/** Offset 0x0579
|
|
**/
|
|
UINT8 UnusedUpdSpace8;
|
|
|
|
/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization
|
|
Range: 0-65535, default is 1000. @warning Do not change from the default
|
|
**/
|
|
UINT16 Gen3SwEqJitterDwellTime;
|
|
|
|
/** Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization
|
|
Range: 0-65535, default is 1. @warning Do not change from the default
|
|
**/
|
|
UINT16 Gen3SwEqJitterErrorTarget;
|
|
|
|
/** Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization
|
|
Range: 0-65535, default is 10000. @warning Do not change from the default
|
|
**/
|
|
UINT16 Gen3SwEqVocDwellTime;
|
|
|
|
/** Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization
|
|
Range: 0-65535, default is 2. @warning Do not change from the default
|
|
**/
|
|
UINT16 Gen3SwEqVocErrorTarget;
|
|
|
|
/** Offset 0x0582 - Panel Power Enable
|
|
Control for enabling/disabling VDD force bit (Required only for early enabling of
|
|
eDP panel). 0=Disable, 1(Default)=Enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PanelPowerEnable;
|
|
|
|
/** Offset 0x0583 - BdatTestType
|
|
Indicates the type of Memory Training data to populate into the BDAT ACPI table.
|
|
0:Rank Marign Tool, 1:Margin2D
|
|
**/
|
|
UINT8 BdatTestType;
|
|
|
|
/** Offset 0x0584 - SaPreMemTestRsvd
|
|
Reserved for SA Pre-Mem Test
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SaPreMemTestRsvd[12];
|
|
|
|
/** Offset 0x0590 - TotalFlashSize
|
|
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
|
|
**/
|
|
UINT16 TotalFlashSize;
|
|
|
|
/** Offset 0x0592 - BiosSize
|
|
Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
|
|
**/
|
|
UINT16 BiosSize;
|
|
|
|
/** Offset 0x0594 - SecurityTestRsvd
|
|
Reserved for SA Pre-Mem Test
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SecurityTestRsvd[4];
|
|
|
|
/** Offset 0x0598 - Smbus dynamic power gating
|
|
Disable or Enable Smbus dynamic power gating.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SmbusDynamicPowerGating;
|
|
|
|
/** Offset 0x0599 - Disable and Lock Watch Dog Register
|
|
Set 1 to clear WDT status, then disable and lock WDT registers.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 WdtDisableAndLock;
|
|
|
|
/** Offset 0x059A - SMBUS SPD Write Disable
|
|
Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
|
|
Disable bit. For security recommendations, SPD write disable bit must be set.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SmbusSpdWriteDisable;
|
|
|
|
/** Offset 0x059B - ChipsetInit HECI message
|
|
Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message.
|
|
If disabled, it prevents from sending ChipsetInit HECI message.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ChipsetInitMessage;
|
|
|
|
/** Offset 0x059C - Bypass ChipsetInit sync reset.
|
|
0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 BypassPhySyncReset;
|
|
|
|
/** Offset 0x059D - Force ME DID Init Status
|
|
Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
|
|
ME DID init stat value
|
|
$EN_DIS
|
|
**/
|
|
UINT8 DidInitStat;
|
|
|
|
/** Offset 0x059E - CPU Replaced Polling Disable
|
|
Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
|
|
$EN_DIS
|
|
**/
|
|
UINT8 DisableCpuReplacedPolling;
|
|
|
|
/** Offset 0x059F - ME DID Message
|
|
Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
|
|
the DID message from being sent)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SendDidMsg;
|
|
|
|
/** Offset 0x05A0 - Retry mechanism for HECI APIs
|
|
Test, 0: disable, 1: enable, Enable/Disable HECI retry.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 DisableHeciRetry;
|
|
|
|
/** Offset 0x05A1 - Check HECI message before send
|
|
Test, 0: disable, 1: enable, Enable/Disable message check.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 DisableMessageCheck;
|
|
|
|
/** Offset 0x05A2 - Skip MBP HOB
|
|
Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SkipMbpHob;
|
|
|
|
/** Offset 0x05A3 - HECI2 Interface Communication
|
|
Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 HeciCommunication2;
|
|
|
|
/** Offset 0x05A4 - Enable KT device
|
|
Test, 0: disable, 1: enable, Enable or Disable KT device.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 KtDeviceEnable;
|
|
|
|
/** Offset 0x05A5
|
|
**/
|
|
UINT8 ReservedFspmTestUpd[11];
|
|
} FSP_M_TEST_CONFIG;
|
|
|
|
/** Fsp M Restricted Configuration
|
|
**/
|
|
typedef struct {
|
|
|
|
/** Offset 0x05B0
|
|
**/
|
|
UINT32 Signature;
|
|
|
|
/** Offset 0x05B4 - Sa Sv Remap Base Override
|
|
SvRemapBaseOverride
|
|
**/
|
|
UINT16 SaSvRemapBaseOverride;
|
|
|
|
/** Offset 0x05B6 - Sa System Agent ClockGating Enable
|
|
SystemAgentClockGatingEnable
|
|
**/
|
|
UINT8 SaSystemAgentClockGatingEnable;
|
|
|
|
/** Offset 0x05B7 - Sa Pcie Pll Shutdown Enable
|
|
PciePllShutdownEnable
|
|
**/
|
|
UINT8 SaPciePllShutdownEnable;
|
|
|
|
/** Offset 0x05B8 - Sa SV_DMI_GEN1_halt
|
|
SV_DMI_GEN1_halt
|
|
**/
|
|
UINT8 SaSV_DMI_GEN1_halt;
|
|
|
|
/** Offset 0x05B9 - Sa SV_nFTS_DMI_auto
|
|
SV_nFTS_DMI_auto
|
|
**/
|
|
UINT8 SaSV_nFTS_DMI_auto;
|
|
|
|
/** Offset 0x05BA - Sa Sv DMI_nFTS
|
|
SvDMI_nFTS
|
|
**/
|
|
UINT8 SaSvDMI_nFTS;
|
|
|
|
/** Offset 0x05BB - Sa nFTS_auto
|
|
nFTS_auto
|
|
**/
|
|
UINT8 SanFTS_auto;
|
|
|
|
/** Offset 0x05BC - Sa SvPEG_nFTS
|
|
SvPEG_nFTS
|
|
**/
|
|
UINT8 SaSvPEG_nFTS[4];
|
|
|
|
/** Offset 0x05C0 - Sa SvPEG_gen3_ccFTS
|
|
SvPEG_gen3_ccFTS
|
|
**/
|
|
UINT8 SaSvPEG_gen3_ccFTS[4];
|
|
|
|
/** Offset 0x05C4 - Sa SvPEG_gen3_nccFTS
|
|
SvPEG_gen3_nccFTS
|
|
**/
|
|
UINT8 SaSvPEG_gen3_nccFTS[4];
|
|
|
|
/** Offset 0x05C8 - Sa nFTS_gen3_auto
|
|
nFTS_gen3_auto
|
|
**/
|
|
UINT8 SanFTS_gen3_auto;
|
|
|
|
/** Offset 0x05C9 - Sa SVIAER
|
|
SVIAER
|
|
**/
|
|
UINT8 SaSVIAER;
|
|
|
|
/** Offset 0x05CA - Sa Sv Scrambler Dmi
|
|
SvScramblerDmi
|
|
**/
|
|
UINT8 SaSvScramblerDmi;
|
|
|
|
/** Offset 0x05CB
|
|
**/
|
|
UINT8 UnusedUpdSpace9[1];
|
|
|
|
/** Offset 0x05CC - Sa Sv Scrambler Peg
|
|
SvScramblerPeg
|
|
**/
|
|
UINT8 SaSvScramblerPeg[4];
|
|
|
|
/** Offset 0x05D0 - Sa Sv Dmi Serr
|
|
SvDmiSerr
|
|
**/
|
|
UINT8 SaSvDmiSerr;
|
|
|
|
/** Offset 0x05D1
|
|
**/
|
|
UINT8 UnusedUpdSpace10[3];
|
|
|
|
/** Offset 0x05D4 - Sa Sv Scrambler Peg Gen3
|
|
SvScramblerPegGen3
|
|
**/
|
|
UINT8 SaSvScramblerPegGen3[4];
|
|
|
|
/** Offset 0x05D8 - Sa Sv Peg Serr
|
|
SvPegSerr
|
|
**/
|
|
UINT8 SaSvPegSerr[4];
|
|
|
|
/** Offset 0x05DC - Sa Test Tx ClkGating
|
|
TestTxClkGating
|
|
**/
|
|
UINT8 SaTestTxClkGating;
|
|
|
|
/** Offset 0x05DD - Sa Test Rx ClkGating
|
|
TestRxClkGating
|
|
**/
|
|
UINT8 SaTestRxClkGating;
|
|
|
|
/** Offset 0x05DE - Sa Test Low Pwr Mode
|
|
TestLowPwrMode
|
|
**/
|
|
UINT8 SaTestLowPwrMode;
|
|
|
|
/** Offset 0x05DF - Sa Sr Mode
|
|
SrMode
|
|
**/
|
|
UINT8 SaSrMode;
|
|
|
|
/** Offset 0x05E0 - Sa Sr Seq
|
|
SrSeq
|
|
**/
|
|
UINT8 SaSrSeq;
|
|
|
|
/** Offset 0x05E1 - Sa Burst Spacing
|
|
BurstSpacing
|
|
**/
|
|
UINT8 SaBurstSpacing;
|
|
|
|
/** Offset 0x05E2 - SvPolicyEnable
|
|
Enable: SV policy is enabled, Disable(Default): SV policy is disabled
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SaRestrictedSvPolicyEnable;
|
|
|
|
/** Offset 0x05E3 - Cpu Sv Boot Mode
|
|
0: Auto (Default), 1: Commercial boot mode, 2: SV boot mode, 3: SV boot JTAG mode
|
|
with SB loop, 4: SV boot JTAG mode without SB loop
|
|
0: Auto , 1: Commercial boot mode, 2: SV boot mode, 3: SV boot JTAG mode with SB
|
|
loop, 4: SV boot JTAG mode without SB loop
|
|
**/
|
|
UINT8 SaCpuSvBootMode;
|
|
|
|
/** Offset 0x05E4 - CpuSvBootMode
|
|
Enable: FlexCon is enabled, Disble(Default): FlexCon is disabled
|
|
$EN_DIS
|
|
**/
|
|
UINT8 XmlCliEnable;
|
|
|
|
/** Offset 0x05E5 - LoadValidationFv
|
|
Enable: Enable loading of ValidationFV, Disable(Default)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 LoadValidationFv;
|
|
|
|
/** Offset 0x05E6 - SvReserveMemoryBelowPrmrr
|
|
Enable: Enable reserve SV memory below PMRR, Disable(Default)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SvReserveMemoryBelowPrmrr;
|
|
|
|
/** Offset 0x05E7 - Sa Test Sample Part Status Override
|
|
0-Passthrough, 1-Production part, 2-Preproduction part
|
|
**/
|
|
UINT8 SaTestSamplePartStatusOverride;
|
|
|
|
/** Offset 0x05E8 - Sa Test Grunit ClockGating
|
|
Enable Sa Test Grunit ClockGating
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SaTestGrunitClockGating;
|
|
|
|
/** Offset 0x05E9 - Sa Test Dmi Cap Reg Lock
|
|
DMI Capability Register Lock
|
|
**/
|
|
UINT8 SaTestDmiCapRegLock;
|
|
|
|
/** Offset 0x05EA - Sa Test Dmi Max Payload Size
|
|
DMI Max Payload Size
|
|
**/
|
|
UINT8 SaTestDmiMaxPayloadSize;
|
|
|
|
/** Offset 0x05EB - Sa Pcie VcLim Lock
|
|
Lock bit
|
|
**/
|
|
UINT8 SaPcieVcLimLock;
|
|
|
|
/** Offset 0x05EC - Sa Pcie VCm Cmp Lim
|
|
VCm Completions override
|
|
**/
|
|
UINT8 SaPcieVCmCmpLim;
|
|
|
|
/** Offset 0x05ED - Sa Pcie VCm PLim
|
|
posted VCm Requests override
|
|
**/
|
|
UINT8 SaPcieVCmPLim;
|
|
|
|
/** Offset 0x05EE - Sa Pcie VCm NpLim
|
|
non-posted VCm Requests override
|
|
**/
|
|
UINT8 SaPcieVCmNpLim;
|
|
|
|
/** Offset 0x05EF - Sa Laguna Credit WA
|
|
Laguna Credit WA
|
|
**/
|
|
UINT8 SaLagunaCreditWA;
|
|
|
|
/** Offset 0x05F0 - Sa Sv Dmi Compliance Deemphasis
|
|
SvDmiComplianceDeemphasis
|
|
**/
|
|
UINT8 SaSvDmiComplianceDeemphasis;
|
|
|
|
/** Offset 0x05F1 - Prefetch NonPrefetch Ratio
|
|
0: All prefetch, 1: Seven of Eight Prefetch, 2: Three of Four Prefetch, 3: Half
|
|
Prefetch Half Non-Prefetch(Default), 4: Three of Four Non-Prefetch, 5: Seven of
|
|
Eight Prefetch, 6: All Non-prefetch
|
|
0: All prefetch, 1: Seven of Eight Prefetch, 2: Three of Four Prefetch, 3: Half
|
|
Prefetch Half Non-Prefetch, 4: Three of Four Non-Prefetch, 5: Seven of Eight Prefetch,
|
|
6: All Non-prefetch
|
|
**/
|
|
UINT8 PrefetchNonPrefetchRatio;
|
|
|
|
/** Offset 0x05F2 - SaPreMemRestrictedRsvd
|
|
Reserved for SA Pre-Mem Restricted
|
|
$EN_DIS
|
|
**/
|
|
UINT8 SaPreMemRestrictedRsvd[30];
|
|
|
|
/** Offset 0x0610 - MSEG Size
|
|
MSEG Size. Valid values 0 : 512K , 1 : 1M , 2 : 1.5M , 3 : 2M , 4 : 2.4M , 5 : 3M
|
|
0 : 512K , 1 : 1M , 2 : 1.5M , 3 : 2M , 4 : 2.4M , 5 : 3M
|
|
**/
|
|
UINT64 MsegSize;
|
|
|
|
/** Offset 0x0618 - Force TXT Enable
|
|
Force TXT Enable; 0: disable, 1: enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ForceTxtEnable;
|
|
|
|
/** Offset 0x0619 - SaPreMemRestrictedRsvd
|
|
Reserved for SA Pre-Mem Restricted
|
|
$EN_DIS
|
|
**/
|
|
UINT8 CpuPreMemRestrictedRsvd[23];
|
|
|
|
/** Offset 0x0630 - Dmi Test Tran Co Over En
|
|
Enable/Disable Lane Transmitter Coefficient.
|
|
**/
|
|
UINT8 PchTestDmiTranCoOverEn[4];
|
|
|
|
/** Offset 0x0634 - Dmi Test Tran Co Over Post Cur
|
|
Lane Transmitter Post-Cursor Coefficient Override.
|
|
**/
|
|
UINT8 PchTestDmiTranCoOverPostCur[4];
|
|
|
|
/** Offset 0x0638 - Dmi Test Tran Co Over Pre Cur
|
|
Lane Transmitter Pre-Cursor Coefficient Override.
|
|
**/
|
|
UINT8 PchTestDmiTranCoOverPreCur[4];
|
|
|
|
/** Offset 0x063C - Dmi Test Up Port Tran Preset
|
|
Upstream Port Lane Transmitter Preset.
|
|
**/
|
|
UINT8 PchTestDmiUpPortTranPreset[4];
|
|
|
|
/** Offset 0x0640 - Dmi Test UpPort Tran Preset En
|
|
0: POR setting, 1: force enable, 2: force disable.
|
|
**/
|
|
UINT8 PchTestDmiUpPortTranPresetEn;
|
|
|
|
/** Offset 0x0641 - Dmi Test Rtlepceb
|
|
DMI Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass (RTLEPCEB).
|
|
**/
|
|
UINT8 PchTestDmiRtlepceb;
|
|
|
|
/** Offset 0x0642 - DMI ME UMA Root Space Check
|
|
DMI IOSF Root Space attribute check for RS3 for cycles targeting MEUMA.
|
|
0: POR, 1: enable, 2: disable
|
|
**/
|
|
UINT8 PchTestDmiMeUmaRootSpaceCheck;
|
|
|
|
/** Offset 0x0643 - ModPhy Selection Policy
|
|
ModPhy Selection for ChipsetInitTable
|
|
**/
|
|
UINT8 ModPhySelection;
|
|
|
|
/** Offset 0x0644 - HECI Communication
|
|
Test, 0: POR, 1: enable, 2: disable, Disables HECI communication causing ME to enter
|
|
error state.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 HeciCommunication;
|
|
|
|
/** Offset 0x0645 - HECI3 Interface Communication
|
|
Test, 0: POR, 1: enable, 2: disable, Adds or Removes HECI3 Device from PCI space.
|
|
$EN_DIS
|
|
**/
|
|
UINT8 HeciCommunication3;
|
|
|
|
/** Offset 0x0646 - Notification test for Host Reset
|
|
Test, 0: POR, 1: enable, 2: disable, Enable test for notification when Host Reset
|
|
$EN_DIS
|
|
**/
|
|
UINT8 HostResetNotification;
|
|
|
|
/** Offset 0x0647 - Send Manufacturing Reset And Halt On S3 Resume
|
|
Test, 0: POR, 1: enable, 2: disable, Enable sending Manufacturing Reset and Halt
|
|
on S3 Resume
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ManufRstAndHaltOnS3Resume;
|
|
|
|
/** Offset 0x0648 - Force Unlock AES
|
|
0(Default)=Disable, 1=Enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ForceUnlockAes;
|
|
|
|
/** Offset 0x0649 - PreMemRestrictedRsvd2
|
|
Reserved for Pre-Mem RestrictedReserved
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PreMemRestrictedRsvd2[23];
|
|
|
|
/** Offset 0x0660 - Asynchronous ODT
|
|
This option configures the Memory Controler Asynchronous ODT control
|
|
0:Enabled, 1:Disabled
|
|
**/
|
|
UINT8 AsyncOdtDis;
|
|
|
|
/** Offset 0x0661 - Power Down Mode
|
|
This option controls command bus tristating during idle periods
|
|
0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
|
|
**/
|
|
UINT8 PowerDownMode;
|
|
|
|
/** Offset 0x0662 - Time Measure
|
|
Time Measure: 0(Default)=Disable, 1=Enable
|
|
$EN_DIS
|
|
**/
|
|
UINT8 MrcTimeMeasure;
|
|
|
|
/** Offset 0x0663 - DLL Weak Lock Support
|
|
Enables/Disable DLL Weak Lock Support
|
|
$EN_DIS
|
|
**/
|
|
UINT8 WeaklockEn;
|
|
|
|
/** Offset 0x0664 - Fore 1 DPC config
|
|
Enables/Disable Fore 1 DPC config
|
|
$EN_DIS
|
|
**/
|
|
UINT8 Force1Dpc;
|
|
|
|
/** Offset 0x0665 - Fore Single Rank config
|
|
Enables/Disable Fore Single Rank config
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ForceSingleRank;
|
|
|
|
/** Offset 0x0666 - SelfRefresh IdleTimer
|
|
SelfRefresh IdleTimer, Default is 512
|
|
**/
|
|
UINT16 SrefCfgIdleTmr;
|
|
|
|
/** Offset 0x0668 - Strong Weak Leaker
|
|
Strong Weak Leaker value. 7=def
|
|
**/
|
|
UINT8 StrongWkLeaker;
|
|
|
|
/** Offset 0x0669
|
|
**/
|
|
UINT8 MrcRestrictedRsvd0x0669[1];
|
|
|
|
/** Offset 0x066A - Opportunistic Read
|
|
Enables/Disable Opportunistic Read (Def= Enable)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 OpportunisticRead;
|
|
|
|
/** Offset 0x066B - Stacked Mode
|
|
Memory Stacked Mode Support (Def = Disable)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 MemStackMode;
|
|
|
|
/** Offset 0x066C - Stacked Mode Ch Bit
|
|
Channel hash bit used during Stacked Mode(Def= BIT28)
|
|
0:BIT28, 1:BIT29, 2:BIT30, 3:BIT31, 4:BIT32, 5:BIT33, 6:BIT34
|
|
**/
|
|
UINT8 StackModeChBit;
|
|
|
|
/** Offset 0x066D - Low Memory Channel
|
|
Selecting which Physical Channel is mapped to low memory.
|
|
0:Channel A, 1:Channel B
|
|
**/
|
|
UINT8 LowMemChannel;
|
|
|
|
/** Offset 0x066E - Cycle Bypass Support
|
|
Enables/Disable Cycle Bypass Support(Def=Disable)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 Disable2CycleBypass;
|
|
|
|
/** Offset 0x066F - MC Register Offset
|
|
Apply user offsets to select MC registers(Def=Disable)
|
|
$EN_DIS
|
|
**/
|
|
UINT8 MCREGOFFSET;
|
|
|
|
/** Offset 0x0670 - CA Vref Ctl Offset
|
|
Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.CAVref
|
|
0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0,
|
|
13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11,
|
|
24:+12, 0xFF:RANDOM
|
|
**/
|
|
UINT8 CAVrefCtlOffset;
|
|
|
|
/** Offset 0x0671 - Ch0 DQ Vref Ctrl Offset
|
|
Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch0VrefCtl
|
|
0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0,
|
|
13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11,
|
|
24:+12, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch0VrefCtlOffset;
|
|
|
|
/** Offset 0x0672 - Ch1 DQ Vref Ctrl Offset
|
|
Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch1VrefCtl
|
|
0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0,
|
|
13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11,
|
|
24:+12, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch1VrefCtlOffset;
|
|
|
|
/** Offset 0x0673 - Ch0 Clk PI Code Offset
|
|
Offset to be applied to DDRCLKCH0_CR_DDRCRCLKPICODE.PiSettingRank[0-3]
|
|
0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch0ClkPiCodeOffset;
|
|
|
|
/** Offset 0x0674 - Ch1 Clk PI Code Offset
|
|
Offset to be applied to DDRCLKCH1_CR_DDRCRCLKPICODE.PiSettingRank[0-3]
|
|
0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch1ClkPiCodeOffset;
|
|
|
|
/** Offset 0x0675 - Ch0 RcvEn Offset
|
|
Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RcvEn
|
|
0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch0RcvEnOffset;
|
|
|
|
/** Offset 0x0676 - Ch1 RcvEn Offset
|
|
Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.RcvEn
|
|
0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch1RcvEnOffset;
|
|
|
|
/** Offset 0x0677 - Ch0 Rx Dqs Offset
|
|
Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset
|
|
0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch0RxDqsOffset;
|
|
|
|
/** Offset 0x0678 - Ch1 Rx Dqs Offset
|
|
Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset
|
|
0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch1RxDqsOffset;
|
|
|
|
/** Offset 0x0679 - Ch0 Tx Dq Offset
|
|
Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset
|
|
0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch0TxDqOffset;
|
|
|
|
/** Offset 0x067A - Ch1 Tx Dq Offset
|
|
Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset
|
|
0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch1TxDqOffset;
|
|
|
|
/** Offset 0x067B - Ch0 Tx Dqs Offset
|
|
Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset
|
|
0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch0TxDqsOffset;
|
|
|
|
/** Offset 0x067C - Ch1 Tx Dqs Offset
|
|
Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset
|
|
0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch1TxDqsOffset;
|
|
|
|
/** Offset 0x067D - Ch0 Vref Offset
|
|
Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
|
|
0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch0VrefOffset;
|
|
|
|
/** Offset 0x067E - Ch1 Vref Offset
|
|
Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
|
|
0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM
|
|
**/
|
|
UINT8 Ch1VrefOffset;
|
|
|
|
/** Offset 0x067F - tRRSG
|
|
Delay between Read-to-Read commands in the same Bank Group for DDR4 or Same Rank
|
|
for DDR3/LPDDR3. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tRRSG;
|
|
|
|
/** Offset 0x0680 - tRRDG
|
|
Delay between Read-to-Read commands in different Bank Group for DDR4 or Same Rank
|
|
for DDR3/LPDDR3. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tRRDG;
|
|
|
|
/** Offset 0x0681 - tRRDR
|
|
Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tRRDR;
|
|
|
|
/** Offset 0x0682 - tRRDD
|
|
Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tRRDD;
|
|
|
|
/** Offset 0x0683 - tWRSG
|
|
Delay between Write-to-Read commands in the same Bank Group for DDR4 or Same Rank
|
|
for DDR3/LPDDR3. 0-Auto, Range 4-86.
|
|
**/
|
|
UINT8 tWRSG;
|
|
|
|
/** Offset 0x0684 - tWRDG
|
|
Delay between Write-to-Read commands in different Bank Group for DDR4 or Same Rank
|
|
for DDR3/LPDDR3. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tWRDG;
|
|
|
|
/** Offset 0x0685 - tWRDR
|
|
Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tWRDR;
|
|
|
|
/** Offset 0x0686 - tWRDD
|
|
Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tWRDD;
|
|
|
|
/** Offset 0x0687 - tWWSG
|
|
Delay between Write-to-Write commands in the same Bank Group for DDR4 or Same Rank
|
|
for DDR3/LPDDR3. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tWWSG;
|
|
|
|
/** Offset 0x0688 - tWWDG
|
|
Delay between Write-to-Write commands in different Bank Group for DDR4 or Same Rank
|
|
for DDR3/LPDDR3. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tWWDG;
|
|
|
|
/** Offset 0x0689 - tWWDR
|
|
Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tWWDR;
|
|
|
|
/** Offset 0x068A - tWWDD
|
|
Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tWWDD;
|
|
|
|
/** Offset 0x068B - tRWSG
|
|
Delay between Read-to-Write commands in the same Bank Group for DDR4 or Same Rank
|
|
for DDR3/LPDDR3. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tRWSG;
|
|
|
|
/** Offset 0x068C - tRWDG
|
|
Delay between Read-to-Write commands in different Bank Group for DDR4 or Same Rank
|
|
for DDR3/LPDDR3. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tRWDG;
|
|
|
|
/** Offset 0x068D - tRWDR
|
|
Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tRWDR;
|
|
|
|
/** Offset 0x068E - tRWDD
|
|
Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
|
|
**/
|
|
UINT8 tRWDD;
|
|
|
|
/** Offset 0x068F - DCTT Test
|
|
Select which test to run
|
|
0:Basic walking memory test, 1:Row Hammer test
|
|
**/
|
|
UINT8 DcttTest;
|
|
|
|
/** Offset 0x0690 - DCTT: Iterations on Row
|
|
Number of repetitions on a Row
|
|
**/
|
|
UINT8 DcttRhIterationOnRow;
|
|
|
|
/** Offset 0x0691 - Page Close Delay Prompt
|
|
SubSequence Delay value used to ensure the page closes (In DClks)
|
|
**/
|
|
UINT8 DcttRhPageCloseDelay;
|
|
|
|
/** Offset 0x0692 - Row Hammer Refresh
|
|
Enable/Disables refreshes during the Row Hammer Test
|
|
$EN_DIS
|
|
**/
|
|
UINT8 DcttRhRefreshEnable;
|
|
|
|
/** Offset 0x0693 - Data Base
|
|
Select which data pattern that is used as the base pattern
|
|
0:Zeros, 1:Ones, 2:Five, 3:A
|
|
**/
|
|
UINT8 DcttDataBase;
|
|
|
|
/** Offset 0x0694 - DCTT: Row Hammer Count
|
|
Number of Hammers for a given Row.
|
|
**/
|
|
UINT32 DcttRhHammerCount;
|
|
|
|
/** Offset 0x0698 - Row swizzle
|
|
Select which Row swizzle algorithm to use during Row Hammer test
|
|
0:No Swizzle, 1:3xOr1_3xOr2, 2:01234567EFCDAB89
|
|
**/
|
|
UINT8 DcttRowSwizzleType;
|
|
|
|
/** Offset 0x0699 - Refresh Multiplier
|
|
Multiplier applied to tREFI
|
|
**/
|
|
UINT8 DcttRefreshMultiplier;
|
|
|
|
/** Offset 0x069A - Bank Disable Mask
|
|
Bit Mask Bank Disable for per-Bank tests (Row Hammer)
|
|
**/
|
|
UINT8 DcttBankDisableMask;
|
|
|
|
/** Offset 0x069B - Clock Gate AB
|
|
Clock Gate AB
|
|
0:Disable, 1:2 Cycles, 2:3 Cycles, 3:4 Cycles
|
|
**/
|
|
UINT8 ScramClockGateAB;
|
|
|
|
/** Offset 0x069C - Clock Gate C
|
|
Select which Row swizzle algorithm to use during Row Hammer test
|
|
0:Disable, 1:2 Cycles, 2:4 Cycles, 3:8 Cycles
|
|
**/
|
|
UINT8 ScramClockGateC;
|
|
|
|
/** Offset 0x069D - Enable DBI AB
|
|
Enable DBI AB
|
|
$EN_DIS
|
|
**/
|
|
UINT8 ScramEnableDbiAB;
|
|
|
|
/** Offset 0x069E - MRC Interpreter
|
|
Select CMOS location match of DD01 or Ctrl-Break key or force entry
|
|
0:CMOS, 1:Break, 2:Force
|
|
**/
|
|
UINT8 Interpreter;
|
|
|
|
/** Offset 0x069F - ODT mode
|
|
ODT mode
|
|
0:Default, 1:Ctt, 2:Vtt, 3:Vddq, 4:Vss,5:Max
|
|
**/
|
|
UINT8 IoOdtMode;
|
|
|
|
/** Offset 0x06A0 - Lock DPR register
|
|
Lock DPR register. <b>0: Platform POR </b>; 1: Enable; 2: Disable
|
|
0:Platform POR, 1: Enable, 2: Disable
|
|
**/
|
|
UINT8 TestMenuDprLock;
|
|
|
|
/** Offset 0x06A1 - PerBankRefresh
|
|
Control of Per Bank Refresh feature for LPDDR DRAMs
|
|
$EN_DIS
|
|
**/
|
|
UINT8 PerBankRefresh;
|
|
|
|
/** Offset 0x06A2 - Command Tristate
|
|
Enables/Disable Command Tristate
|
|
$EN_DIS
|
|
**/
|
|
UINT8 CmdTriStateDis;
|
|
|
|
/** Offset 0x06A3
|
|
**/
|
|
UINT8 MrcRestrictedRsvd[1];
|
|
|
|
/** Offset 0x06A4
|
|
**/
|
|
UINT8 ReservedFspmRestrictedUpd[26];
|
|
} FSP_M_RESTRICTED_CONFIG;
|
|
|
|
/** Fsp M UPD Configuration
|
|
**/
|
|
typedef struct {
|
|
|
|
/** Offset 0x0000
|
|
**/
|
|
FSP_UPD_HEADER FspUpdHeader;
|
|
|
|
/** Offset 0x0020
|
|
**/
|
|
FSPM_ARCH_UPD FspmArchUpd;
|
|
|
|
/** Offset 0x0040
|
|
**/
|
|
FSP_M_CONFIG FspmConfig;
|
|
|
|
/** Offset 0x0520
|
|
**/
|
|
FSP_M_TEST_CONFIG FspmTestConfig;
|
|
|
|
/** Offset 0x05B0
|
|
**/
|
|
FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;
|
|
|
|
/** Offset 0x06BE
|
|
**/
|
|
UINT16 UpdTerminator;
|
|
} FSPM_UPD;
|
|
|
|
#pragma pack()
|
|
|
|
#endif
|