236 lines
9.1 KiB
C
236 lines
9.1 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* mt3.c
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*
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* Common Technology functions for DDR3
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: (Mem/Tech/DDR3)
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* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
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*
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**/
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/*****************************************************************************
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*
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* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ***************************************************************************
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*
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*/
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/*
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*----------------------------------------------------------------------------
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* MODULES USED
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*
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*----------------------------------------------------------------------------
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*/
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#include "AGESA.h"
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#include "Ids.h"
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#include "mm.h"
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#include "mn.h"
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#include "mu.h"
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#include "mt.h"
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#include "mt3.h"
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#include "mtspd3.h"
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#include "mtot3.h"
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#include "OptionMemory.h"
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#include "PlatformMemoryConfiguration.h"
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#include "Filecode.h"
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CODE_GROUP (G1_PEICC)
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RDATA_GROUP (G1_PEICC)
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/* features */
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#define FILECODE PROC_MEM_TECH_DDR3_MT3_FILECODE
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/*----------------------------------------------------------------------------
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* DEFINITIONS AND MACROS
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*
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*----------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------
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* TYPEDEFS AND STRUCTURES
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*
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*----------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------
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* PROTOTYPES OF LOCAL FUNCTIONS
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*
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*----------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------
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* EXPORTED FUNCTIONS
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*
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*----------------------------------------------------------------------------
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*/
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/* -----------------------------------------------------------------------------*/
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/**
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*
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* This function Constructs the technology block
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*
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* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
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* @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
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*
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*/
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BOOLEAN
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MemConstructTechBlock3 (
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IN OUT MEM_TECH_BLOCK *TechPtr,
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IN OUT MEM_NB_BLOCK *NBPtr
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)
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{
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TECHNOLOGY_TYPE *TechTypePtr;
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UINT8 Dct;
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UINT8 Channel;
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UINT8 i;
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DIE_STRUCT *MCTPtr;
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DCT_STRUCT *DCTPtr;
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CH_DEF_STRUCT *ChannelPtr;
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UINT8 DimmSlots;
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TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0, 0, NULL, NULL);
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if (TechTypePtr != NULL) {
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// Ensure the platform override value is valid
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ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
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if (*TechTypePtr != DDR3_TECHNOLOGY) {
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return FALSE;
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}
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}
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TechPtr->NBPtr = NBPtr;
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TechPtr->RefPtr = NBPtr->RefPtr;
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MCTPtr = NBPtr->MCTPtr;
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TechPtr->SendAllMRCmds = MemTSendAllMRCmds3;
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TechPtr->FreqChgCtrlWrd = FreqChgCtrlWrd3;
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TechPtr->SetDramMode = MemTSetDramMode3;
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TechPtr->DimmPresence = MemTDIMMPresence3;
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TechPtr->SpdCalcWidth = MemTSPDCalcWidth3;
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TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed3;
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TechPtr->AutoCycTiming = MemTAutoCycTiming3;
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TechPtr->SpdSetBanks = MemTSPDSetBanks3;
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TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
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TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr3;
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TechPtr->AdjustTwrwr = MemTAdjustTwrwr3;
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TechPtr->AdjustTwrrd = MemTAdjustTwrrd3;
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TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer3;
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TechPtr->GetLD = MemTGetLD3;
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TechPtr->MaxFilterDly = 0;
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//
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// Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
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// The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
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//
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// DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
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// (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop
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// on this array only)
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// 2 DIMMS PER CHANNEL
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//
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// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
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// Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
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// DimmSpdPtr[2]------->NULL
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// DimmSpdPtr[3]------->NULL
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//
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// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
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// Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
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// | DimmSpdPtr[2]------->NULL
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// +----DimmSpdPtr[3]
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//
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// Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0]
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// Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1]
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// +-- | ---DimmSpdPtr[2]
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// +----DimmSpdPtr[3]
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//
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// 3 DIMMS PER CHANNEL
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//
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// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
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// Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
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// Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
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// DimmSpdPtr[3]------->NULL
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//
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// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
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// Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
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// Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
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// +----DimmSpdPtr[3]
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//
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//
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// FOR LRDIMMS
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//
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// This code will assign SPD pointers on the basis of Physical ranks, even though
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// an LRDIMM may only use one or two logical ranks, that determination will have to
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// be made from downstream code. An LRDIMM with greater than 2 Physical ranks will have
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// its DimmSpdPtr[] mapped as if it were a QR in the above diagrams.
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for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
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NBPtr->SwitchDCT (NBPtr, Dct);
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DCTPtr = NBPtr->DCTPtr;
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for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
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NBPtr->SwitchChannel (NBPtr, Channel);
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ChannelPtr = NBPtr->ChannelPtr;
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ChannelPtr->TechType = DDR3_TECHNOLOGY;
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ChannelPtr->MCTPtr = MCTPtr;
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ChannelPtr->DCTPtr = DCTPtr;
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DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
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MCTPtr->SocketId,
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NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
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);
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//
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// Initialize the SPD pointers for each Dimm
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//
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for (i = 0 ; i < ARRAY_SIZE(ChannelPtr->DimmSpdPtr); i++) {
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ChannelPtr->DimmSpdPtr[i] = NULL;
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}
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for (i = 0 ; i < DimmSlots; i++) {
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ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
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if ( (i + 2) < ARRAY_SIZE(ChannelPtr->DimmSpdPtr)) {
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if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
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if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) {
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ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
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}
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}
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}
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}
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}
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}
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// Initialize Common technology functions
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MemTCommonTechInit (TechPtr);
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return TRUE;
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}
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/*----------------------------------------------------------------------------
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* LOCAL FUNCTIONS
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*
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*----------------------------------------------------------------------------
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*/
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