226 lines
7.7 KiB
C
226 lines
7.7 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* PCIe init tables.
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*
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*
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: GNB
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* @e \$Revision: 85361 $ @e \$Date: 2013-01-07 11:15:28 -0600 (Mon, 07 Jan 2013) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ***************************************************************************
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*
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*/
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#include "AGESA.h"
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#include "Gnb.h"
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#include "GnbPcie.h"
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#include "GnbRegistersKB.h"
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* P R O T O T Y P E S O F L O C A L F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* T A B L E S
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*----------------------------------------------------------------------------------------
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*/
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STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = {
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_4440_ADDRESS),
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D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_MASK,
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0x2 << D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_OFFSET
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},
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_4450_ADDRESS),
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D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_MASK |
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D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_MASK,
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(0x0 << D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_OFFSET) | (0x90 << D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_OFFSET)
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},
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_0004_ADDRESS),
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D0F0xE4_PHY_0004_CfgIdleDetTh_MASK,
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0x0 << D0F0xE4_PHY_0004_CfgIdleDetTh_OFFSET
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}
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};
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CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableKB = {
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&PcieInitEarlyTable[0],
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ARRAY_SIZE(PcieInitEarlyTable)
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};
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STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = {
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{
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D0F0xE4_CORE_0020_ADDRESS,
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D0F0xE4_CORE_0020_CiRcOrderingDis_MASK |
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D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK,
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(0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET)
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},
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{
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D0F0xE4_CORE_0010_ADDRESS,
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D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_MASK,
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(0x4 << D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_OFFSET)
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},
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{
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D0F0xE4_CORE_001C_ADDRESS,
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D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK |
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D0F0xE4_CORE_001C_TxArbSlvLimit_MASK |
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D0F0xE4_CORE_001C_TxArbMstLimit_MASK,
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(0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) |
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(0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) |
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(0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET)
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},
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{
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D0F0xE4_CORE_0040_ADDRESS,
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D0F0xE4_CORE_0040_PElecIdleMode_MASK,
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(0x1 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET)
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},
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{
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D0F0xE4_CORE_0002_ADDRESS,
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D0F0xE4_CORE_0002_HwDebug_0_MASK,
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(0x1 << D0F0xE4_CORE_0002_HwDebug_0_OFFSET)
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},
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{
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D0F0xE4_CORE_00C1_ADDRESS,
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D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK |
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D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK,
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(0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) |
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(0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET)
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},
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{
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D0F0xE4_CORE_00B0_ADDRESS,
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D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK |
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D0F0xE4_CORE_00B0_StrapF0AerEn_MASK,
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(0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET) | (0x0 << D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET)
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}
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};
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CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableKB = {
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&CoreInitTable[0],
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ARRAY_SIZE(CoreInitTable)
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};
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STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = {
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{
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DxFxxE4_x70_ADDRESS,
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DxFxxE4_x70_RxRcbCplTimeoutMode_MASK,
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(0x1 << DxFxxE4_x70_RxRcbCplTimeoutMode_OFFSET)
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},
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{
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DxFxxE4_xA0_ADDRESS,
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DxFxxE4_xA0_Lc16xClearTxPipe_MASK | DxFxxE4_xA0_LcL1ImmediateAck_MASK | DxFxxE4_xA0_LcL0sInactivity_MASK,
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(0x1 << DxFxxE4_xA0_Lc16xClearTxPipe_OFFSET) |
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(0x1 << DxFxxE4_xA0_LcL1ImmediateAck_OFFSET) |
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(0x6 << DxFxxE4_xA0_LcL0sInactivity_OFFSET)
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},
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{
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DxFxxE4_xA1_ADDRESS,
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DxFxxE4_xA1_LcDontGotoL0sifL1Armed_MASK,
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(0x1 << DxFxxE4_xA1_LcDontGotoL0sifL1Armed_OFFSET)
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},
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{
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DxFxxE4_xA2_ADDRESS,
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DxFxxE4_xA2_LcRenegotiateEn_MASK | DxFxxE4_xA2_LcUpconfigureSupport_MASK,
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(0x1 << DxFxxE4_xA2_LcRenegotiateEn_OFFSET) |
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(0x1 << DxFxxE4_xA2_LcUpconfigureSupport_OFFSET)
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},
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{
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DxFxxE4_xA3_ADDRESS,
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DxFxxE4_xA3_LcXmitFtsBeforeRecovery_MASK,
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(0x1 << DxFxxE4_xA3_LcXmitFtsBeforeRecovery_OFFSET)
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},
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{
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DxFxxE4_xB1_ADDRESS,
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DxFxxE4_xB1_LcElecIdleMode_MASK |
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DxFxxE4_xB1_LcDeassertRxEnInL0s_MASK |
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DxFxxE4_xB1_LcBlockElIdleinL0_MASK,
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(0x1 << DxFxxE4_xB1_LcElecIdleMode_OFFSET) |
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(0x1 << DxFxxE4_xB1_LcDeassertRxEnInL0s_OFFSET) |
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(0x1 << DxFxxE4_xB1_LcBlockElIdleinL0_OFFSET)
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},
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{
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0xC0,
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0x70000,
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(0x1 << 16)
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}
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};
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CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableKB = {
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&PortInitEarlyTable[0],
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ARRAY_SIZE(PortInitEarlyTable)
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};
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STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = {
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{
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DxFxxE4_xA2_ADDRESS,
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DxFxxE4_xA2_LcDynLanesPwrState_MASK,
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(0x3 << DxFxxE4_xA2_LcDynLanesPwrState_OFFSET)
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},
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{
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DxFxxE4_x6A_ADDRESS,
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DxFxxE4_x6A_ErrReportingDis_MASK,
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(0x1 << DxFxxE4_x6A_ErrReportingDis_OFFSET)
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},
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// {
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// 0xC0,
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// DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK,
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// (0x1 << DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET)
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// }
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};
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CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableKB = {
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&PortInitMidTable[0],
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ARRAY_SIZE(PortInitMidTable)
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};
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