225 lines
7.3 KiB
C
225 lines
7.3 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* SATA Controller family specific service procedure
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*
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*
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: FCH
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* @e \$Revision: 86583 $ @e \$Date: 2013-01-23 12:31:06 -0600 (Wed, 23 Jan 2013) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ***************************************************************************
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*/
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#include "FchPlatform.h"
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#include "Filecode.h"
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#define FILECODE PROC_FCH_SATA_FAMILY_YANGTZE_YANGTZESATAENVSERVICE_FILECODE
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SATA_PHY_SETTING SataPhyTable[] =
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{
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{0x0030, 0x0040F407},
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{0x0120, 0x00403204},
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{0x0110, 0x00403103},
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{0x0031, 0x0040F407},
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{0x0121, 0x00403204},
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{0x0111, 0x00403103},
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};
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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//
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// Local Routine
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//
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VOID FchSataCombineControlDataByte (IN UINT8 *ControlReg);
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VOID FchSataCombineControlDataWord (IN UINT16 *ControlReg);
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/**
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* FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space
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* register setting
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*
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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VOID
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FchInitEnvProgramSataPciRegs (
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IN VOID *FchDataPtr
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)
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{
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UINT8 *PortRegByte;
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UINT16 *PortRegWord;
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FCH_DATA_BLOCK *LocalCfgPtr;
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AMD_CONFIG_PARAMS *StdHeader;
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LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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StdHeader = LocalCfgPtr->StdHeader;
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//
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//Caculate SataPortReg for SATA_ESP_PORT
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//
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PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg);
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FchSataCombineControlDataByte (PortRegByte);
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PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg);
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FchSataCombineControlDataByte (PortRegByte);
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PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode);
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FchSataCombineControlDataWord (PortRegWord);
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PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg);
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FchSataCombineControlDataByte (PortRegByte);
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//
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// Set Sata PCI Configuration Space Write enable
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//
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SataEnableWriteAccess (StdHeader);
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// *
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// Enables the SATA watchdog timer register prior to the SATA BIOS post
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//
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RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44), AccessWidth8, 0xff, BIT0, StdHeader);
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// *
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// SATA PCI Watchdog timer setting
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// Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
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//
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RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44 + 2), AccessWidth8, 0, 0x20, StdHeader);
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//
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// BIT4: Enable fast boot (SpeedupXPBoot)
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//
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RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040), AccessWidth8, 0xef, 0, StdHeader);
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RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, 0xff, BIT7, StdHeader);
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//
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// Unused SATA Ports Disabled
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//
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RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader);
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RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
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}
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/**
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* FchSataCombineControlDataByte - Combine port control options
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* to one control byte.
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*
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*
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* @param[in] *ControlReg - Data pointer for control byte.
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*
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*/
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VOID
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FchSataCombineControlDataByte (
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IN UINT8 *ControlReg
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)
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{
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UINT8 Index;
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UINT8 PortControl;
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*ControlReg = 0;
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for ( Index = 0; Index < 8; Index++ ) {
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PortControl = *( ControlReg + 1 + Index );
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*ControlReg |= PortControl << Index;
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}
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}
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/**
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* FchSataCombineControlDataWord - Combine port control options
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* to one control Word.
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*
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*
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* @param[in] *ControlReg - Data pointer for control byte.
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*
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*/
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VOID
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FchSataCombineControlDataWord (
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IN UINT16 *ControlReg
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)
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{
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UINT8 Index;
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UINT8 PortControl;
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*ControlReg = 0;
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for ( Index = 0; Index < 8; Index++ ) {
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PortControl = *( (UINT8 *)ControlReg + 2 + Index );
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*ControlReg |= PortControl << (Index * 2);
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}
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}
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/**
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* FchProgramSataPhy - Program Sata PHY registers
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*
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* @param[in] StdHeader
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*
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*/
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VOID
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FchProgramSataPhy (
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IN AMD_CONFIG_PARAMS *StdHeader
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)
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{
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SATA_PHY_SETTING *PhyTablePtr;
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UINT16 Index;
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UINT32 SquelchValue[2];
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UINT8 PortNum;
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PhyTablePtr = &SataPhyTable[0];
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for (Index = 0; Index < ARRAY_SIZE(SataPhyTable); Index++) {
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RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0xFC00, PhyTablePtr->PhyCoreControlWord, StdHeader);
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RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader);
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++PhyTablePtr;
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}
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SquelchValue[0] = (0x07 << 9);
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SquelchValue[1] = (0x07 << 9);
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for (PortNum = 0; PortNum < 2; PortNum ++) {
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RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader);
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RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
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RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 13)), (UINT32) (0x0 << 13), StdHeader);
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RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x20 + PortNum), StdHeader);
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RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
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RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x10 + PortNum), StdHeader);
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RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
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RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, 0x010, StdHeader);
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}
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}
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