490 lines
16 KiB
C
490 lines
16 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* Config Fch HwAcpi controller
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*
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* Init HwAcpi Controller features.
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: FCH
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* @e \$Revision: 87262 $ @e \$Date: 2013-01-31 09:13:43 -0600 (Thu, 31 Jan 2013) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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****************************************************************************
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*/
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#include "FchPlatform.h"
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#include "amdlib.h"
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#include "cpuServices.h"
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#include "Filecode.h"
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#define FILECODE PROC_FCH_HWACPI_FAMILY_YANGTZE_YANGTZEHWACPIENVSERVICE_FILECODE
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#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID
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ACPI_REG_WRITE FchYangtzeInitEnvSpecificHwAcpiMmioTable[] =
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{
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{00, 00, 0xB0, 0xAC},
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{PMIO_BASE >> 8, FCH_PMIOA_REG28, (UINT8)~(BIT0 + BIT2), BIT0}, // Set ASF SMBUS master function enabled here (temporary)
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#ifdef ACPI_SLEEP_TRAP
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{SMI_BASE >> 8, FCH_SMI_REGB0, (UINT8)~(BIT2 + BIT3), BIT2}, // Set SLP_TYPE as SMI event
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{PMIO_BASE >> 8, FCH_PMIOA_REGBE, (UINT8)~BIT5, 0x00}, // Disabled SLP function for S1/S3/S4/S5
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{PMIO_BASE >> 8, 0x08 + 3, (UINT8)~(BIT0 + BIT1), BIT1}, // Set S state transition disabled (BIT0) force ACPI to
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// send SMI message when writing to SLP_TYP Acpi register. (BIT1)
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{SMI_BASE >> 8, FCH_SMI_REG98 + 3, (UINT8)~BIT7, 0x00}, // Enabled Global Smi ( BIT7 clear as 0 to enable )
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#endif
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{PMIO_BASE >> 8, 0x80 + 1, (UINT8)~(BIT3 + BIT4), BIT3 + BIT4},
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{0xFF, 0xFF, 0xFF, 0xFF},
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};
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/**
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* FchInitEnvHwAcpiMmioTable - Fch ACPI MMIO initial
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* during POST.
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*
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*/
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ACPI_REG_WRITE FchYangtzeInitEnvHwAcpiMmioTable[] =
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{
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{00, 00, 0xB0, 0xAC}, /// Signature
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//
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// HPET workaround
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//
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{PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7},
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{PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00},
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{PMIO_BASE >> 8, FCH_PMIOA_REGC4, (UINT8)~BIT2, BIT2},
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{PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0x3D},
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{PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x0, 0x04},
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{PMIO_BASE >> 8, FCH_PMIOA_REGC2, 0x20, 0x58},
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{PMIO_BASE >> 8, FCH_PMIOA_REGC2 + 1, 0, 0x40},
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{PMIO_BASE >> 8, FCH_PMIOA_REGC2, (UINT8)~(BIT4), BIT4},
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{PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x03},
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{PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
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{PMIO_BASE >> 8, 0x74 + 3, (UINT8)~BIT5, 0},
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{PMIO_BASE >> 8, FCH_PMIOA_REGBA, (UINT8)~BIT3, BIT3},
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{PMIO_BASE >> 8, FCH_PMIOA_REGBC, (UINT8)~BIT1, BIT1},
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{PMIO_BASE >> 8, 0xDC, 0x7C, BIT1},
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{SMI_BASE >> 8, FCH_SMI_Gevent1, 0, 1},
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{SMI_BASE >> 8, FCH_SMI_Gevent3, 0, 3},
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{SMI_BASE >> 8, FCH_SMI_Gevent4, 0, 4},
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{SMI_BASE >> 8, FCH_SMI_Gevent5, 0, 5},
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{SMI_BASE >> 8, FCH_SMI_Gevent6, 0, 6},
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{SMI_BASE >> 8, FCH_SMI_Gevent23, 0, 23},
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{SMI_BASE >> 8, FCH_SMI_xHC0Pme, 0, 11},
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{SMI_BASE >> 8, FCH_SMI_xHC1Pme, 0, 11},
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{SMI_BASE >> 8, FCH_SMI_Usbwakup0, 0, 11},
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{SMI_BASE >> 8, FCH_SMI_Usbwakup1, 0, 11},
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{SMI_BASE >> 8, FCH_SMI_Usbwakup2, 0, 11},
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{SMI_BASE >> 8, FCH_SMI_Usbwakup3, 0, 11},
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{SMI_BASE >> 8, FCH_SMI_IMCGevent0, 0, 12},
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{SMI_BASE >> 8, FCH_SMI_FanThGevent, 0, 13},
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{SMI_BASE >> 8, FCH_SMI_SBGppPme0, 0, 15},
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{SMI_BASE >> 8, FCH_SMI_SBGppPme1, 0, 16},
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{SMI_BASE >> 8, FCH_SMI_SBGppPme2, 0, 17},
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{SMI_BASE >> 8, FCH_SMI_SBGppPme3, 0, 18},
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{SMI_BASE >> 8, FCH_SMI_GecPme, 0, 19},
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{SMI_BASE >> 8, FCH_SMI_CIRPme, 0, 28},
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{SMI_BASE >> 8, FCH_SMI_Gevent8, 0, 24},
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// {SMI_BASE >> 8, FCH_SMI_AzaliaPme, 0, 27},
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{SMI_BASE >> 8, FCH_SMI_SataGevent0, 0, 30},
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{SMI_BASE >> 8, FCH_SMI_SataGevent1, 0, 31},
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{SMI_BASE >> 8, FCH_SMI_REG08, 0xE7, 0},
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{SMI_BASE >> 8, FCH_SMI_REG0C + 2, (UINT8)~BIT3, BIT3},
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{SMI_BASE >> 8, FCH_SMI_TWARN, 0, 9},
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{0xFF, 0xFF, 0xFF, 0xFF},
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};
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/**
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* FchYangtzeInitEnvHwAcpiPciTable - PCI device registers initial
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* during early POST.
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*
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*/
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REG8_MASK FchYangtzeInitEnvHwAcpiPciTable[] =
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{
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//
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// SMBUS Device (Bus 0, Dev 20, Func 0)
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//
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{0x00, SMBUS_BUS_DEV_FUN, 0},
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{FCH_CFG_REG10, 0X00, (FCH_VERSION & 0xFF)}, ///Program the version information
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{FCH_CFG_REG11, 0X00, (FCH_VERSION >> 8)},
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{0xFF, 0xFF, 0xFF},
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};
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/**
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* ProgramEnvPFchAcpiMmio - Config HwAcpi MMIO registers
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* Acpi S3 resume won't execute this procedure (POST only)
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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VOID
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ProgramEnvPFchAcpiMmio (
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IN VOID *FchDataPtr
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)
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{
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FCH_DATA_BLOCK *LocalCfgPtr;
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AMD_CONFIG_PARAMS *StdHeader;
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LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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StdHeader = LocalCfgPtr->StdHeader;
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ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchYangtzeInitEnvHwAcpiMmioTable[0]), StdHeader);
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}
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/**
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* ProgramFchEnvHwAcpiPciReg - Config HwAcpi PCI controller
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* before PCI emulation
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*
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*
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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VOID
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ProgramFchEnvHwAcpiPciReg (
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IN VOID *FchDataPtr
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)
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{
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FCH_DATA_BLOCK *LocalCfgPtr;
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AMD_CONFIG_PARAMS *StdHeader;
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LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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StdHeader = LocalCfgPtr->StdHeader;
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//
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//Early post initialization of pci config space
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//
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ProgramPciByteTable ((REG8_MASK*) (&FchYangtzeInitEnvHwAcpiPciTable[0]),
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ARRAY_SIZE(FchYangtzeInitEnvHwAcpiPciTable), StdHeader);
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if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) {
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RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader);
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}
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if ( LocalCfgPtr->Misc.NoneSioKbcSupport ) {
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RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2 + BIT1);
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} else {
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RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2);
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}
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ProgramPcieNativeMode (FchDataPtr);
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}
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/**
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* FchVgaInit - Config VGA CODEC
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*
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* @param[in] VOID empty
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*
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*/
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VOID
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FchVgaInit (
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OUT VOID
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)
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{
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}
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/**
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* ProgramSpecificFchInitEnvAcpiMmio - Config HwAcpi MMIO before
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* PCI emulation
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*
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*
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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VOID
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ProgramSpecificFchInitEnvAcpiMmio (
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IN VOID *FchDataPtr
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)
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{
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CPUID_DATA CpuId;
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FCH_DATA_BLOCK *LocalCfgPtr;
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AMD_CONFIG_PARAMS *StdHeader;
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LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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StdHeader = LocalCfgPtr->StdHeader;
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ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchYangtzeInitEnvSpecificHwAcpiMmioTable[0]), StdHeader);
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LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
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if ((LocalCfgPtr->HwAcpi.AnyHt200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) {
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RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x0A);
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RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x80 + 3, AccessWidth8, 0xFE, 0x28);
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} else {
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RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01);
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RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x80 + 3, AccessWidth8, 0xFE, 0x20);
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}
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG6C + 2, AccessWidth8, 0x5F, 0xA0);
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//
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// Ac Loss Control
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//
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AcLossControl ((UINT8) LocalCfgPtr->HwAcpi.PwrFailShadow);
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//
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// FCH VGA Init
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//
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FchVgaInit ();
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//
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// Set ACPIMMIO by OEM Input table
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//
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ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->HwAcpi.OemProgrammingTablePtr), StdHeader);
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}
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/**
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* ValidateFchVariant - Validate FCH Variant
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*
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*
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*
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* @param[in] FchDataPtr
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*
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*/
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VOID
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ValidateFchVariant (
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IN VOID *FchDataPtr
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)
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{
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CPUID_DATA CpuId;
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FCH_DATA_BLOCK *LocalCfgPtr;
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AMD_CONFIG_PARAMS *StdHeader;
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LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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StdHeader = LocalCfgPtr->StdHeader;
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LibAmdCpuidRead (CPUID_FMF, &CpuId, StdHeader);
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LocalCfgPtr->Misc.FchCpuId = ( UINT32 ) (CpuId.EAX_Reg & 0xFFFFFFFF);
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}
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/**
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* IsExternalClockMode - Is External Clock Mode?
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*
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*
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* @retval TRUE or FALSE
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*
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*/
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BOOLEAN
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IsExternalClockMode (
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IN VOID *FchDataPtr
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)
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{
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UINT8 MISC80;
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ReadMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80 + 2, AccessWidth8, &MISC80);
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return ( (BOOLEAN) ((MISC80 & BIT1) == 0) );
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}
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/**
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* ProgramFchEnvSpreadSpectrum - Config SpreadSpectrum before
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* PCI emulation
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*
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*
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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VOID
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ProgramFchEnvSpreadSpectrum (
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IN VOID *FchDataPtr
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)
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{
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UINT8 PortStatus;
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UINT8 FchSpreadSpectrum;
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FCH_DATA_BLOCK *LocalCfgPtr;
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AMD_CONFIG_PARAMS *StdHeader;
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LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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StdHeader = LocalCfgPtr->StdHeader;
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FchSpreadSpectrum = LocalCfgPtr->HwAcpi.SpreadSpectrum;
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if ( FchSpreadSpectrum ) {
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00);
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if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 0 ) {
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/// -0.362%
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x01);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0xCF5C);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0137);
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}
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if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 1 ) {
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/// -0.375%
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x01);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0xE000);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0142);
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}
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if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 2 ) {
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/// -0.4%
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0158);
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}
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if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 3 ) {
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/// -0.425%
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0x1FFF);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x016D);
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}
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if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 4 ) {
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/// -0.45%
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0x4000);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0183);
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}
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if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 5 ) {
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/// -0.475%
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0x6000);
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0198);
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}
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, BIT0);
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} else {
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00);
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}
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//
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// PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5)
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// OSC Clock setting for internal clock generator mode (BIT6)
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//
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GetChipSysMode (&PortStatus, StdHeader);
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if ( ((PortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG04 + 1, AccessWidth8, (UINT32)~(BIT5 + BIT6), BIT5 + BIT6);
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}
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}
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/**
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* TurnOffCG2
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*
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*
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* @retval VOID
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*
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*/
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VOID
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TurnOffCG2 (
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OUT VOID
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)
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{
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}
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/**
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* BackUpCG2
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*
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*
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* @retval VOID
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*
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*/
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VOID
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BackUpCG2 (
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OUT VOID
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)
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{
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}
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/**
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* HpetInit - Program Fch HPET function
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*
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*
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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|
VOID
|
|
HpetInit (
|
|
IN VOID *FchDataPtr
|
|
)
|
|
{
|
|
DESCRIPTION_HEADER *HpetTable;
|
|
UINT8 FchHpetTimer;
|
|
UINT8 FchHpetMsiDis;
|
|
FCH_DATA_BLOCK *LocalCfgPtr;
|
|
|
|
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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|
FchHpetTimer = (UINT8) LocalCfgPtr->Hpet.HpetEnable;
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|
FchHpetMsiDis = (UINT8) LocalCfgPtr->Hpet.HpetMsiDis;
|
|
|
|
HpetTable = NULL;
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|
if ( FchHpetTimer == TRUE ) {
|
|
//
|
|
//Program the HPET BAR address
|
|
//
|
|
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, LocalCfgPtr->Hpet.HpetBase);
|
|
|
|
//
|
|
//Enabling decoding of HPET MMIO
|
|
//Enable HPET MSI support
|
|
//Enable High Precision Event Timer (also called Multimedia Timer) interrupt
|
|
//
|
|
if ( FchHpetMsiDis == FALSE ) {
|
|
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1 + BIT2 + BIT3 + BIT4);
|
|
#ifdef FCH_TIMER_TICK_INTERVAL_WA
|
|
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1);
|
|
#endif
|
|
} else {
|
|
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1);
|
|
}
|
|
|
|
} else {
|
|
if ( ! (LocalCfgPtr->Misc.S3Resume) ) {
|
|
HpetTable = (DESCRIPTION_HEADER*) AcpiLocateTable (Int32FromChar('H','P','E','T'));//'TEPH'
|
|
}
|
|
if ( HpetTable != NULL ) {
|
|
HpetTable->Signature = Int32FromChar('T','E','P','H');//'HPET'
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ProgramPcieNativeMode - Config Pcie Native Mode
|
|
*
|
|
*
|
|
*
|
|
* @param[in] FchDataPtr Fch configuration structure pointer.
|
|
*
|
|
*/
|
|
VOID
|
|
ProgramPcieNativeMode (
|
|
IN VOID *FchDataPtr
|
|
)
|
|
{
|
|
UINT8 FchNativepciesupport;
|
|
FCH_DATA_BLOCK *LocalCfgPtr;
|
|
|
|
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
|
|
FchNativepciesupport = (UINT8) LocalCfgPtr->Misc.NativePcieSupport;
|
|
|
|
//
|
|
// PCIE Native setting
|
|
//
|
|
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBA + 1, AccessWidth8, (UINT32)~BIT6, 0);
|
|
if ( FchNativepciesupport == 1) {
|
|
RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x74 + 3, AccessWidth8, (UINT32)~(BIT3 + BIT1 + BIT0), BIT3 + BIT0);
|
|
} else {
|
|
RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x74 + 3, AccessWidth8, (UINT32)~(BIT3 + BIT1 + BIT0), BIT3);
|
|
}
|
|
}
|