232 lines
7.8 KiB
C
232 lines
7.8 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* PCIe late post initialization.
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*
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*
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: GNB
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* @e \$Revision: 65061 $ @e \$Date: 2012-02-06 23:48:39 -0600 (Mon, 06 Feb 2012) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ***************************************************************************
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*
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*/
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#include "AGESA.h"
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#include "Gnb.h"
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#include "GnbPcie.h"
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#include "PcieComplexDataTN.h"
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#include "GnbRegistersTN.h"
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* P R O T O T Y P E S O F L O C A L F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* T A B L E S
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*----------------------------------------------------------------------------------------
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*/
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STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = {
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{
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WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS),
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D0F0xE4_WRAP_8016_CalibAckLatency_MASK,
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0
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},
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{
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PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
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D0F0xE4_PHY_2008_VdDetectEn_MASK,
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0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
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},
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{
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PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
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D0F0xE4_PHY_2008_VdDetectEn_MASK,
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0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
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},
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{
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PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS),
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D0F0xE4_PHY_2008_VdDetectEn_MASK,
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0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
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},
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{
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PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
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D0F0xE4_PHY_2008_VdDetectEn_MASK,
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0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
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},
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{
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PHY_SPACE (DDI2_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
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D0F0xE4_PHY_2008_VdDetectEn_MASK,
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0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
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}
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};
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CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN = {
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&PcieInitEarlyTable[0],
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ARRAY_SIZE(PcieInitEarlyTable)
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};
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STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = {
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{
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D0F0xE4_CORE_0020_ADDRESS,
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D0F0xE4_CORE_0020_CiRcOrderingDis_MASK |
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D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK,
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(0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET)
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},
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{
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D0F0xE4_CORE_0010_ADDRESS,
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D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK,
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(0x4 << D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET)
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},
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{
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D0F0xE4_CORE_001C_ADDRESS,
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D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK |
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D0F0xE4_CORE_001C_TxArbSlvLimit_MASK |
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D0F0xE4_CORE_001C_TxArbMstLimit_MASK,
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(0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) |
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(0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) |
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(0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET)
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},
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{
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D0F0xE4_CORE_0040_ADDRESS,
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D0F0xE4_CORE_0040_PElecIdleMode_MASK,
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(0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET)
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},
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{
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D0F0xE4_CORE_0002_ADDRESS,
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D0F0xE4_CORE_0002_HwDebug_0__MASK,
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(0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET)
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},
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{
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D0F0xE4_CORE_00C1_ADDRESS,
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D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK |
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D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK,
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(0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) |
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(0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET)
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},
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{
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D0F0xE4_CORE_00B0_ADDRESS,
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D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK,
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(0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET)
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}
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};
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CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN = {
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&CoreInitTable[0],
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ARRAY_SIZE(CoreInitTable)
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};
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STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = {
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{
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DxF0xE4_x02_ADDRESS,
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DxF0xE4_x02_RegsLcAllowTxL1Control_MASK,
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(0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET)
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},
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{
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DxF0xE4_x70_ADDRESS,
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DxF0xE4_x70_RxRcbCplTimeoutMode_MASK,
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(0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET)
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},
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{
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DxF0xE4_xA0_ADDRESS,
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DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK | DxF0xE4_xA0_LcL0sInactivity_MASK,
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(0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) |
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(0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) |
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(0x6 << DxF0xE4_xA0_LcL0sInactivity_OFFSET)
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},
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{
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DxF0xE4_xA1_ADDRESS,
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DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK,
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(0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET)
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},
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{
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DxF0xE4_xA2_ADDRESS,
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DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK,
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(0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) |
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(0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET)
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},
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{
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DxF0xE4_xA3_ADDRESS,
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DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK,
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(0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET)
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},
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{
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DxF0xE4_xB1_ADDRESS,
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DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK,
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(0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) |
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(0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET)
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}
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};
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CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN = {
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&PortInitEarlyTable[0],
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ARRAY_SIZE(PortInitEarlyTable)
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};
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STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = {
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{
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DxF0xE4_xA2_ADDRESS,
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DxF0xE4_xA2_LcDynLanesPwrState_MASK,
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(0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET)
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},
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{
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DxF0xE4_xC0_ADDRESS,
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DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK,
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(0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET)
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}
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};
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CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN = {
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&PortInitMidTable[0],
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ARRAY_SIZE(PortInitMidTable)
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};
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