94 lines
3.4 KiB
C
94 lines
3.4 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* Config Fch LPC controller
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*
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* Init LPC Controller features.
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: FCH
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* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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****************************************************************************
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*/
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#include "FchPlatform.h"
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#include "Filecode.h"
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#define FILECODE PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCENVSERVICE_FILECODE
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/**
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* FchInitHudson2EnvLpcPciTable - PCI device registers initial
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* during early POST.
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*
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*/
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REG8_MASK FchInitHudson2EnvLpcPciTable[] =
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{
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//
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// LPC Device (Bus 0, Dev 20, Func 3)
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//
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{0x00, LPC_BUS_DEV_FUN, 0},
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{FCH_LPC_REG40, (UINT8)~BIT2, BIT2}, /// Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b
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{FCH_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
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{0x78 , 0xFC, 00}, /// Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b / Disables MSI capability
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{FCH_LPC_REGBB, (UINT8)~BIT0, (BIT0 + BIT3 + BIT4 + BIT5)}, /// Enabled SPI Prefetch from HOST.
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{0xFF, 0xFF, 0xFF},
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};
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/**
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* FchInitEnvLpcProgram - Config LPC controller before PCI
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* emulation
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*
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*
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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VOID
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FchInitEnvLpcProgram (
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IN VOID *FchDataPtr
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)
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{
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FCH_DATA_BLOCK *LocalCfgPtr;
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AMD_CONFIG_PARAMS *StdHeader;
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LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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StdHeader = LocalCfgPtr->StdHeader;
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ProgramPciByteTable ((REG8_MASK*) (&FchInitHudson2EnvLpcPciTable[0]),
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ARRAY_SIZE(FchInitHudson2EnvLpcPciTable), StdHeader);
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//
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// Disable LPC A-Link Cycle Bypass
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//
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RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50 + 2, AccessWidth8, 0xF7, BIT3);
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}
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