137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* Config Fch Pcib controller
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*
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* Init Pcib Controller features (PEI phase).
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: FCH
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* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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****************************************************************************
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*/
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#include "FchPlatform.h"
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#define FILECODE PROC_FCH_PCIB_PCIBRESET_FILECODE
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/**
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* FchInitResetPcibPciTable - Pcib device registers initial
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* during the power on stage.
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*
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*
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*
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*
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*/
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REG8_MASK FchInitResetPcibPciTable[] =
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{
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//
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// P2P Bridge (Bus 0, Dev 20, Func 4)
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//
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{0x00, PCIB_BUS_DEV_FUN, 0},
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{FCH_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
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{FCH_PCIB_REG40, 0xDF, 0x20},
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{0x50 , 0x02, 0x01},
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{0xFF, 0xFF, 0xFF},
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};
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/**
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* FchInitResetPcib - Config Pcib controller during Power-On
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*
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*
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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VOID
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FchInitResetPcib (
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IN VOID *FchDataPtr
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)
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{
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AMD_CONFIG_PARAMS *StdHeader;
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StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
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ProgramPciByteTable (
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(REG8_MASK*) (&FchInitResetPcibPciTable[0]),
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ARRAY_SIZE(FchInitResetPcibPciTable),
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StdHeader
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);
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if ( UserOptions.FchBldCfg->CfgFchPort80BehindPcib ) {
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FchInitResetPcibPort80Enable (FchDataPtr);
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}
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}
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/**
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* FchInitResetPcibPort80Enable - Pcib device registers initial
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* during the power on stage.
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*
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*
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*
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*
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*/
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REG8_MASK FchInitResetPcibPort80EnableTable[] =
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{
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//
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// P2P Bridge (Bus 0, Dev 20, Func 4)
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//
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{0x00, PCIB_BUS_DEV_FUN, 0},
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{0x1C , 0x00, 0xF0},
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{0x1D , 0x00, 0x00},
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{0x04 , 0x00, 0x21},
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{0xFF, 0xFF, 0xFF},
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};
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/**
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* FchInitResetPcibPort80Enable - Enable Port80 Behind PCIB
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*
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*
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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VOID
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FchInitResetPcibPort80Enable (
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IN VOID *FchDataPtr
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)
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{
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AMD_CONFIG_PARAMS *StdHeader;
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StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
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ProgramPciByteTable (
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(REG8_MASK*) (&FchInitResetPcibPort80EnableTable[0]),
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ARRAY_SIZE(FchInitResetPcibPort80EnableTable),
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StdHeader
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);
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}
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