109 lines
4.0 KiB
C
109 lines
4.0 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* Config Fch Pcib controller
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*
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* Init Pcib Controller features.
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: FCH
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* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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****************************************************************************
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*/
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#include "FchPlatform.h"
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#define FILECODE PROC_FCH_PCIB_PCIBENV_FILECODE
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/**
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* FchInitEnvPcibPciTable - PCI device registers initial during
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* early POST.
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*
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*/
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REG8_MASK FchInitEnvPcibPciTable[] =
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{
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//
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// PCIB Bridge (Bus 0, Dev 20, Func 4)
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//
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{0x00, PCIB_BUS_DEV_FUN, 0},
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{FCH_PCIB_REG40, 0xFF, BIT5}, /// PCI-bridge Subtractive Decode
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{FCH_PCIB_REG4B, 0xFF, BIT7}, ///
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{0x66 , 0xFF, BIT4}, /// Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
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{0x65 , 0xFF, BIT7}, /// proper operation of CLKRUN#.
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{FCH_PCIB_REG0D, 0x00, 0x40}, /// Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
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{FCH_PCIB_REG1B, 0x00, 0x40}, /// of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
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{FCH_PCIB_REG66 + 1, 0xFF, BIT1}, /// Enable PCI bus GNT3#..
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{0xFF, 0xFF, 0xFF},
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};
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/**
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* FchInitEnvPcib - Config Pcib controller before PCI emulation
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*
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*
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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VOID
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FchInitEnvPcib (
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IN VOID *FchDataPtr
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)
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{
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UINT8 VerbPciClks;
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FCH_DATA_BLOCK *LocalCfgPtr;
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AMD_CONFIG_PARAMS *StdHeader;
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LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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StdHeader = LocalCfgPtr->StdHeader;
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//
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//Early post initialization of pci config space
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//
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ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]),
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ARRAY_SIZE(FchInitEnvPcibPciTable), StdHeader);
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//
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//Disable or Enable PCI Clks based on input
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//
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VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x0F) << 2);
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RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG42, AccessWidth8, (UINT32)~(BIT5 + BIT4 + BIT3 + BIT2), VerbPciClks, StdHeader);
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VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x10) >> 4);
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RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x4A , AccessWidth8, (UINT32)~BIT0, VerbPciClks, StdHeader);
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//
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// PCIB MSI
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//
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if (LocalCfgPtr->Pcib.PcibMsiEnable) {
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RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x40 , AccessWidth8, (UINT32)~BIT3, BIT3, StdHeader);
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}
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}
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