179 lines
6.0 KiB
C
179 lines
6.0 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* Config Fch HwAcpi controller
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*
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* Init HwAcpi Controller features.
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: FCH
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* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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****************************************************************************
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*/
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#include "FchPlatform.h"
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#include "amdlib.h"
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#include "cpuServices.h"
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#include "Filecode.h"
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#define FILECODE PROC_FCH_HWACPI_HWACPILATE_FILECODE
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#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID
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///
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/// PCI_IRQ_REG_BLOCK- FCH PCI IRQ registers block
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///
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typedef struct _PCI_IRQ_REG_BLOCK {
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UINT8 PciIrqIndex; // PciIrqIndex - selects which PCI interrupt to map
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UINT8 PciIrqData; // PciIrqData - Interrupt #
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} PCI_IRQ_REG_BLOCK;
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STATIC PCI_IRQ_REG_BLOCK FchInternalDeviceIrqForApicMode[] = {
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{ (FCH_IRQ_INTA | FCH_IRQ_IOAPIC), 0x10},
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{ (FCH_IRQ_INTB | FCH_IRQ_IOAPIC), 0x11},
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{ (FCH_IRQ_INTC | FCH_IRQ_IOAPIC), 0x12},
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{ (FCH_IRQ_INTD | FCH_IRQ_IOAPIC), 0x13},
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{ (FCH_IRQ_INTE | FCH_IRQ_IOAPIC), 0x14},
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{ (FCH_IRQ_INTF | FCH_IRQ_IOAPIC), 0x15},
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{ (FCH_IRQ_INTG | FCH_IRQ_IOAPIC), 0x16},
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{ (FCH_IRQ_INTH | FCH_IRQ_IOAPIC), 0x17},
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{ (FCH_IRQ_HDAUDIO | FCH_IRQ_IOAPIC), 0x10},
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{ (FCH_IRQ_GEC | FCH_IRQ_IOAPIC), 0x10},
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{ (FCH_IRQ_SD | FCH_IRQ_IOAPIC), 0x10},
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{ (FCH_IRQ_GPPINT0 | FCH_IRQ_IOAPIC), 0x10},
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{ (FCH_IRQ_IDE | FCH_IRQ_IOAPIC), 0x11},
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{ (FCH_IRQ_USB18INTB | FCH_IRQ_IOAPIC), 0x11},
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{ (FCH_IRQ_USB19INTB | FCH_IRQ_IOAPIC), 0x11},
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{ (FCH_IRQ_USB22INTB | FCH_IRQ_IOAPIC), 0x11},
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{ (FCH_IRQ_GPPINT1 + FCH_IRQ_IOAPIC), 0x11},
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{ (FCH_IRQ_USB18INTA | FCH_IRQ_IOAPIC), 0x12},
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{ (FCH_IRQ_USB19INTA | FCH_IRQ_IOAPIC), 0x12},
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{ (FCH_IRQ_USB22INTA | FCH_IRQ_IOAPIC), 0x12},
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{ (FCH_IRQ_USB20INTC | FCH_IRQ_IOAPIC), 0x12},
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{ (FCH_IRQ_GPPINT2 | FCH_IRQ_IOAPIC), 0x12},
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{ (FCH_IRQ_SATA | FCH_IRQ_IOAPIC), 0x13},
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{ (FCH_IRQ_GPPINT3 | FCH_IRQ_IOAPIC), 0x13},
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};
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#define NUM_OF_DEVICE_FOR_APICIRQ ARRAY_SIZE(FchInternalDeviceIrqForApicMode)
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/**
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* FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS.
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*
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* @param[in] FchDataPtr Fch configuration structure pointer.
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*
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*/
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VOID
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FchInitLateHwAcpi (
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IN VOID *FchDataPtr
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)
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{
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FCH_DATA_BLOCK *LocalCfgPtr;
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AMD_CONFIG_PARAMS *StdHeader;
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UINT8 i;
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LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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StdHeader = LocalCfgPtr->StdHeader;
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if ( IsGCPU (LocalCfgPtr) ) {
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GcpuRelatedSetting (LocalCfgPtr);
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} else {
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//TNBU C3PopupSetting (LocalCfgPtr);
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}
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// Mt C1E Enable
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MtC1eEnable (LocalCfgPtr);
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if (LocalCfgPtr->Gpp.SerialDebugBusEnable == TRUE ) {
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RwMem (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + FCH_SDB_REG00, AccessWidth8, 0xFF, 0x05);
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}
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StressResetModeLate (LocalCfgPtr);
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SbSleepTrapControl (FALSE); /* TODO: Checkout if we need to disable sleep trap in Non-SMI mode. */
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for (i = 0; i < NUM_OF_DEVICE_FOR_APICIRQ; i++) {
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LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &FchInternalDeviceIrqForApicMode[i].PciIrqIndex, StdHeader);
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LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &FchInternalDeviceIrqForApicMode[i].PciIrqData, StdHeader);
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}
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}
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/**
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* IsGCPU - Is Gcpu Cpu?
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*
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*
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* @retval TRUE or FALSE
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*
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*/
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BOOLEAN
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IsGCPU (
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IN VOID *FchDataPtr
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)
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{
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UINT8 ExtendedFamily;
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UINT8 ExtendedModel;
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UINT8 BaseFamily;
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UINT8 BaseModel;
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UINT8 Stepping;
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UINT8 Family;
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UINT8 Model;
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CPUID_DATA CpuId;
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FCH_DATA_BLOCK *LocalCfgPtr;
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AMD_CONFIG_PARAMS *StdHeader;
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LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
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StdHeader = LocalCfgPtr->StdHeader;
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LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
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ExtendedFamily = (UINT8) ((CpuId.EAX_Reg >> 20) & 0xff);
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ExtendedModel = (UINT8) ((CpuId.EAX_Reg >> 16) & 0xf);
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BaseFamily = (UINT8) ((CpuId.EAX_Reg >> 8) & 0xf);
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BaseModel = (UINT8) ((CpuId.EAX_Reg >> 4) & 0xf);
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Stepping = (UINT8) ((CpuId.EAX_Reg >> 0) & 0xf);
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Family = BaseFamily + ExtendedFamily;
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Model = (ExtendedModel << 4) + BaseModel;
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if ( (Family == 0x12) || \
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(Family == 0x14) || \
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(Family == 0x16) ) {
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return TRUE;
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} else {
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return FALSE;
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}
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}
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