376 lines
12 KiB
C
376 lines
12 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* Pre-training PCIe subsystem initialization routines.
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*
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*
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: GNB
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* @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2011, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* ***************************************************************************
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*
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*/
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#include "AGESA.h"
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#include "Ids.h"
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#include "Gnb.h"
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#include "GnbPcie.h"
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#include "GnbPcieFamServices.h"
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#include "PcieFamilyServices.h"
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#include "PcieInit.h"
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#include "PcieMiscLib.h"
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#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
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#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
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#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1)
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#include "GnbRegistersON.h"
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#include "Filecode.h"
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#define FILECODE PROC_GNB_PCIE_PCIEINIT_FILECODE
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* P R O T O T Y P E S O F L O C A L F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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VOID
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PcieCommonCoreInit (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN PCIe_PLATFORM_CONFIG *Pcie
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);
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AGESA_STATUS
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PcieInitSrbmCallback (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN OUT VOID *Buffer,
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IN PCIe_PLATFORM_CONFIG *Pcie
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);
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AGESA_STATUS
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PcieInitCallback (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN OUT VOID *Buffer,
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IN PCIe_PLATFORM_CONFIG *Pcie
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);
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AGESA_STATUS
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PciePostInitCallback (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN OUT VOID *Buffer,
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IN PCIe_PLATFORM_CONFIG *Pcie
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);
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/*----------------------------------------------------------------------------------------*/
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/**
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* Control port visibility in PCI config space
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*
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*
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* @param[in] Control Make port Hide/Unhide ports
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* @param[in] Pcie Pointer to global PCIe configuration
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*/
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VOID
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PciePortsVisibilityControl (
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IN PCIE_PORT_VISIBILITY Control,
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IN PCIe_PLATFORM_CONFIG *Pcie
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)
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{
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PCIe_COMPLEX_CONFIG *ComplexList;
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ComplexList = &Pcie->ComplexList[0];
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while (ComplexList != NULL) {
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PCIe_SILICON_CONFIG *SiliconList;
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SiliconList = PcieComplexGetSiliconList (ComplexList);
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while (SiliconList != NULL) {
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PcieFmPortVisabilityControl (Control, SiliconList, Pcie);
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SiliconList = PcieLibGetNextDescriptor (SiliconList);
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}
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ComplexList = PcieLibGetNextDescriptor (ComplexList);
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}
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}
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PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = {
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{
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D0F0xE4_CORE_0020_ADDRESS,
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D0F0xE4_CORE_0020_CiRcOrderingDis_MASK,
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(0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET)
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},
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{
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0x10,
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0x1c00,
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(0x4 << 10)
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},
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{
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D0F0xE4_CORE_001C_ADDRESS,
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D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK |
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D0F0xE4_CORE_001C_TxArbSlvLimit_MASK |
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D0F0xE4_CORE_001C_TxArbMstLimit_MASK,
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(0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) |
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(0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) |
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(0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET)
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},
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{
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D0F0xE4_CORE_0040_ADDRESS,
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D0F0xE4_CORE_0040_PElecIdleMode_MASK,
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(0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET)
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},
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{
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D0F0xE4_CORE_0002_ADDRESS,
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D0F0xE4_CORE_0002_HwDebug_0__MASK,
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(0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET)
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},
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{
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D0F0xE4_CORE_00C1_ADDRESS,
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D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK |
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D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK,
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(0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) |
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(0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET)
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},
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{
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D0F0xE4_CORE_00B0_ADDRESS,
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D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK,
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(0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET)
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}
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};
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/*----------------------------------------------------------------------------------------*/
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/**
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* Common Core Init
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*
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*
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* @param[in] Wrapper Pointer to wrapper configuration descriptor
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* @param[in] Pcie Pointer to global PCIe configuration
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*/
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VOID
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PcieCommonCoreInit (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN PCIe_PLATFORM_CONFIG *Pcie
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)
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{
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UINT8 CoreId;
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UINTN Index;
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if (PcieLibIsPcieWrapper (Wrapper)) {
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IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n");
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for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
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for (Index = 0; Index < ARRAY_SIZE(CoreInitTable); Index++) {
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UINT32 Value;
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Value = PcieRegisterRead (
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Wrapper,
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CORE_SPACE (CoreId, CoreInitTable[Index].Reg),
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Pcie
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);
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Value &= (~CoreInitTable[Index].Mask);
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Value |= CoreInitTable[Index].Data;
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PcieRegisterWrite (
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Wrapper,
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CORE_SPACE (CoreId, CoreInitTable[Index].Reg),
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Value,
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FALSE,
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Pcie
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);
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}
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}
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IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Exit\n");
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}
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers.
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*
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*
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* @param[in] Wrapper Pointer to wrapper configuration descriptor
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* @param[in] Buffer Pointer buffer
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* @param[in] Pcie Pointer to global PCIe configuration
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*/
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AGESA_STATUS
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PcieInitSrbmCallback (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN OUT VOID *Buffer,
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IN PCIe_PLATFORM_CONFIG *Pcie
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)
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{
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PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
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return AGESA_SUCCESS;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Per wrapper Pcie Init prior training.
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*
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*
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* @param[in] Wrapper Pointer to wrapper configuration descriptor
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* @param[in] Buffer Pointer buffer
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* @param[in] Pcie Pointer to global PCIe configuration
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*/
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AGESA_STATUS
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PcieInitCallback (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN OUT VOID *Buffer,
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IN PCIe_PLATFORM_CONFIG *Pcie
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)
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{
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AGESA_STATUS Status;
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PcieTopologyPrepareForReconfig (Wrapper, Pcie);
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Status = PcieTopologySetCoreConfig (Wrapper, Pcie);
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ASSERT (Status == AGESA_SUCCESS);
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PcieTopologyApplyLaneMux (Wrapper, Pcie);
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PcieFmPifSetRxDetectPowerMode (Wrapper, Pcie);
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PciePifSetLs2ExitTime (Wrapper, Pcie);
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PcieTopologySelectMasterPll (Wrapper, Pcie);
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PcieTopologyExecuteReconfig (Wrapper, Pcie);
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PcieTopologySetLinkReversal (Wrapper, Pcie);
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PciePifApplyGanging (Wrapper, Pcie);
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PcieFmPhyApplyGanging (Wrapper, Pcie);
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PciePifPllInitForDdi (Wrapper, Pcie);
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PcieTopologyLaneControl (
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DisableLanes,
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PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, LANE_TYPE_PCIE_ALLOCATED, Wrapper, Pcie),
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Wrapper,
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Pcie
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);
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PcieSetDdiOwnPhy (Wrapper, Pcie);
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PciePollPifForCompeletion (Wrapper, Pcie);
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PcieFmAvertClockPickers (Wrapper, Pcie);
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PcieFmConfigureClock (PcieGen1, Wrapper, Pcie);
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PcieCommonCoreInit (Wrapper, Pcie);
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PciePifDisableFifoReset (Wrapper, Pcie);
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return Status;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Pcie Init
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*
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*
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*
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* @param[in] Pcie Pointer to global PCIe configuration
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* @retval AGESA_SUCCESS Topology successfully mapped
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* @retval AGESA_ERROR Topology can not be mapped
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*/
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AGESA_STATUS
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PcieInit (
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IN PCIe_PLATFORM_CONFIG *Pcie
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)
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{
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AGESA_STATUS Status;
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AGESA_STATUS AgesaStatus;
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IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Enter\n");
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AgesaStatus = AGESA_SUCCESS;
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Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallback, NULL, Pcie);
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AGESA_STATUS_UPDATE (Status, AgesaStatus);
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PcieFmPreInit (Pcie);
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Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitCallback, NULL, Pcie);
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AGESA_STATUS_UPDATE (Status, AgesaStatus);
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PcieFmSetBootUpVoltage (PcieGen1, Pcie);
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IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Exit [%x]\n", AgesaStatus);
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return AgesaStatus;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Per wrapper Pcie Init prior training.
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*
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*
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* @param[in] Wrapper Pointer to wrapper configuration descriptor
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* @param[in] Buffer Pointer buffer
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* @param[in] Pcie Pointer to global PCIe configuration
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*/
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AGESA_STATUS
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PciePostInitCallback (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN OUT VOID *Buffer,
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IN PCIe_PLATFORM_CONFIG *Pcie
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)
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{
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AGESA_STATUS Status;
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Status = AGESA_SUCCESS;
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PcieFmConfigureClock (
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PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie),
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Wrapper,
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Pcie
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);
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return Status;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Pcie Init
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*
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*
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*
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* @param[in] Pcie Pointer to global PCIe configuration
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* @retval AGESA_SUCCESS Topology successfully mapped
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* @retval AGESA_ERROR Topology can not be mapped
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*/
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AGESA_STATUS
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PciePostInit (
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IN PCIe_PLATFORM_CONFIG *Pcie
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)
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{
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AGESA_STATUS Status;
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AGESA_STATUS AgesaStatus;
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IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Enter\n");
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AgesaStatus = AGESA_SUCCESS;
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Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_PCIE_WRAPPER, PciePostInitCallback, NULL, Pcie);
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AGESA_STATUS_UPDATE (Status, AgesaStatus);
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PcieFmSetBootUpVoltage (
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PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie),
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Pcie
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);
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IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus);
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return AgesaStatus;
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}
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