681 lines
22 KiB
C
681 lines
22 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* Family specific PCIe wrapper configuration services
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*
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*
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: GNB
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* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2011, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* ***************************************************************************
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*
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*/
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#include "AGESA.h"
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#include "Ids.h"
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#include "Gnb.h"
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#include "GnbPcie.h"
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#include "PcieFamilyServices.h"
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#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
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#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
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#include "PcieMiscLib.h"
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#include "GnbPcieFamServices.h"
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#include "OntarioDefinitions.h"
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#include "GnbRegistersON.h"
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#include "NbSmuLib.h"
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#include "Filecode.h"
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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extern BUILD_OPT_CFG UserOptions;
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* P R O T O T Y P E S O F L O C A L F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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AGESA_STATUS
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STATIC
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PcieOnConfigureGppEnginesLaneAllocation (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN UINT8 ConfigurationId
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);
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AGESA_STATUS
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STATIC
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PcieOnConfigureDdiEnginesLaneAllocation (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN UINT8 ConfigurationId
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);
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VOID
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PcieFmExecuteNativeGen1Reconfig (
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IN PCIe_PLATFORM_CONFIG *Pcie
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);
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AGESA_STATUS
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PcieOnGetGppConfigurationValue (
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IN UINT64 ConfigurationSignature,
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OUT UINT8 *ConfigurationValue
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);
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/*----------------------------------------------------------------------------------------
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* T A B L E S
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*----------------------------------------------------------------------------------------
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*/
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PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = {
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_6440_ADDRESS),
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D0F0xE4_PHY_6440_RxInCalForce_MASK,
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0x1 << D0F0xE4_PHY_6440_RxInCalForce_OFFSET
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},
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_6480_ADDRESS),
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D0F0xE4_PHY_6480_RxInCalForce_MASK,
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0x1 << D0F0xE4_PHY_6480_RxInCalForce_OFFSET
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},
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_6500_ADDRESS),
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D0F0xE4_PHY_6500_RxInCalForce_MASK,
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0x1 << D0F0xE4_PHY_6500_RxInCalForce_OFFSET
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},
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_6600_ADDRESS),
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D0F0xE4_PHY_6600_RxInCalForce_MASK,
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0x1 << D0F0xE4_PHY_6600_RxInCalForce_OFFSET
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},
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_6840_ADDRESS),
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D0F0xE4_PHY_6840_RxInCalForce_MASK,
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0x1 << D0F0xE4_PHY_6840_RxInCalForce_OFFSET
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},
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_6880_ADDRESS),
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D0F0xE4_PHY_6880_RxInCalForce_MASK,
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0x1 << D0F0xE4_PHY_6880_RxInCalForce_OFFSET
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},
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_6900_ADDRESS),
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D0F0xE4_PHY_6900_RxInCalForce_MASK,
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0x1 << D0F0xE4_PHY_6900_RxInCalForce_OFFSET
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},
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_6A00_ADDRESS),
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D0F0xE4_PHY_6A00_RxInCalForce_MASK,
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0x1 << D0F0xE4_PHY_6A00_RxInCalForce_OFFSET
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},
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{
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WRAP_SPACE (0, D0F0xE4_WRAP_8016_ADDRESS),
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D0F0xE4_WRAP_8016_CalibAckLatency_MASK,
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0
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},
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{
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PHY_SPACE (0, 0, D0F0xE4_PHY_4004_ADDRESS),
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D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_MASK | D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_MASK,
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(0x1 << D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_OFFSET) | (0x1 << D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_OFFSET)
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},
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{
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D0F0xE4_x0108_8071_ADDRESS,
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D0F0xE4_x0108_8071_RxAdjust_MASK,
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0x3 << D0F0xE4_x0108_8071_RxAdjust_OFFSET
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},
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{
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D0F0xE4_x0108_8072_ADDRESS,
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D0F0xE4_x0108_8072_TxAdjust_MASK,
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0x3 << D0F0xE4_x0108_8072_TxAdjust_OFFSET
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},
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};
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/*----------------------------------------------------------------------------------------*/
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/**
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* Configure engine list to support lane allocation according to configuration ID.
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*
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*
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*
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* @param[in] Wrapper Pointer to wrapper config descriptor
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* @param[in] EngineType Engine Type
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* @param[in] ConfigurationId Configuration ID
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* @retval AGESA_SUCCESS Configuration successfully applied
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* @retval AGESA_UNSUPPORTED No more configuration available for given engine type
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* @retval AGESA_ERROR Requested configuration not supported
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*/
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AGESA_STATUS
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PcieFmConfigureEnginesLaneAllocation (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN PCIE_ENGINE_TYPE EngineType,
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IN UINT8 ConfigurationId
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)
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{
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AGESA_STATUS Status;
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Status = AGESA_ERROR;
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switch (Wrapper->WrapId) {
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case GPP_WRAP_ID:
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if (EngineType != PciePortEngine) {
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return AGESA_UNSUPPORTED;
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}
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Status = PcieOnConfigureGppEnginesLaneAllocation (Wrapper, ConfigurationId);
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break;
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case DDI_WRAP_ID:
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if (EngineType != PcieDdiEngine) {
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return AGESA_UNSUPPORTED;
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}
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Status = PcieOnConfigureDdiEnginesLaneAllocation (Wrapper, ConfigurationId);
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break;
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default:
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ASSERT (FALSE);
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}
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return Status;
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}
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CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = {
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//4 5 6 7 8 (SB)
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{4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3},
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{4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3},
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{4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3},
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{4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3},
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{4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3},
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{4, 4, 5, 5, 6, 6, 7, 7, 0, 3}
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};
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CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = {
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//4 5 6 7 8 (SB)
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{1, 2, 3, 4, 0},
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{1, 2, 3, 4, 0},
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{1, 3, 2, 4, 0},
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{1, 2, 3, 4, 0},
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{1, 4, 2, 3, 0},
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{1, 2, 3, 4, 0}
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};
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/*----------------------------------------------------------------------------------------*/
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/**
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* Configure GFX engine list to support lane allocation according to configuration ID.
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*
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*
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*
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* @param[in] Wrapper Pointer to wrapper config descriptor
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* @param[in] ConfigurationId Configuration ID
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* @retval AGESA_SUCCESS Configuration successfully applied
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* @retval AGESA_ERROR Requested configuration not supported
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*/
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AGESA_STATUS
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STATIC
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PcieOnConfigureGppEnginesLaneAllocation (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN UINT8 ConfigurationId
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)
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{
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PCIe_ENGINE_CONFIG *EnginesList;
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UINTN CoreLaneIndex;
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UINTN PortIdIndex;
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if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) {
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return AGESA_ERROR;
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}
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EnginesList = PcieWrapperGetEngineList (Wrapper);
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CoreLaneIndex = 0;
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PortIdIndex = 0;
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do {
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if (PortIdIndex > 0) EnginesList++;
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EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED;
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EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++];
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EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
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EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
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} while (IS_LAST_DESCRIPTOR (EnginesList));
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return AGESA_SUCCESS;
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}
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CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = {
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{0, 3, 4, 7, 8, 11}
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};
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/*----------------------------------------------------------------------------------------*/
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/**
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* Configure DDI engine list to support lane allocation according to configuration ID.
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*
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*
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*
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* @param[in] Wrapper Pointer to wrapper config descriptor
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* @param[in] ConfigurationId Configuration ID
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* @retval AGESA_SUCCESS Configuration successfully applied
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* @retval AGESA_ERROR Requested configuration not supported
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*/
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AGESA_STATUS
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STATIC
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PcieOnConfigureDdiEnginesLaneAllocation (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN UINT8 ConfigurationId
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)
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{
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PCIe_ENGINE_CONFIG *EnginesList;
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UINTN LaneIndex;
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EnginesList = PcieWrapperGetEngineList (Wrapper);
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if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) {
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return AGESA_ERROR;
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}
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LaneIndex = 0;
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do {
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if (LaneIndex > 0) EnginesList++;
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EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED;
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EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] +
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Wrapper->StartPhyLane;
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EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] +
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Wrapper->StartPhyLane;
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} while (IS_LAST_DESCRIPTOR (EnginesList));
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return AGESA_SUCCESS;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Configure clock to run out of the wrapper at specific speed
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*
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*
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* @param[in] LinkSpeedCapability Link Speed capability
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* @param[in] Wrapper Pointer to wrapper config descriptor
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* @param[in] Pcie Pointer to global PCIe configuration
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*/
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VOID
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PcieFmConfigureClock (
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IN PCIE_LINK_SPEED_CAP LinkSpeedCapability,
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN PCIe_PLATFORM_CONFIG *Pcie
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)
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{
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Get configuration Value for GPP wrapper
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*
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*
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*
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* @param[in] ConfigurationSignature Configuration signature
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* @param[out] ConfigurationValue Configuration value
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* @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue
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* @retval AGESA_ERROR ConfigurationSignature is incorrect
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*/
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AGESA_STATUS
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PcieOnGetGppConfigurationValue (
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IN UINT64 ConfigurationSignature,
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OUT UINT8 *ConfigurationValue
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)
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{
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switch (ConfigurationSignature) {
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case GPP_CORE_x4x1x1x1x1:
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*ConfigurationValue = 0x4;
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break;
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case GPP_CORE_x4x2x1x1:
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case GPP_CORE_x4x2x1x1_ST:
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//Configuration 2:1:1 - Device Numbers 4:5:6
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//Configuration 2:1:1 - Device Numbers 4:6:7
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*ConfigurationValue = 0x3;
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break;
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case GPP_CORE_x4x2x2:
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case GPP_CORE_x4x2x2_ST:
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//Configuration 2:2 - Device Numbers 4:5
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//Configuration 2:2 - Device Numbers 4:6
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*ConfigurationValue = 0x2;
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break;
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case GPP_CORE_x4x4:
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*ConfigurationValue = 0x1;
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break;
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default:
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ASSERT (FALSE);
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return AGESA_ERROR;
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}
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return AGESA_SUCCESS;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Get core configuration value
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*
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*
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*
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* @param[in] Wrapper Pointer to internal configuration data area
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* @param[in] CoreId Core ID
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* @param[in] ConfigurationSignature Configuration signature
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* @param[out] ConfigurationValue Configuration value (for core configuration)
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* @retval AGESA_SUCCESS Configuration successfully applied
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* @retval AGESA_ERROR Core configuration value can not be determined
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*/
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AGESA_STATUS
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PcieFmGetCoreConfigurationValue (
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IN PCIe_WRAPPER_CONFIG *Wrapper,
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IN UINT8 CoreId,
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IN UINT64 ConfigurationSignature,
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IN UINT8 *ConfigurationValue
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)
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{
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AGESA_STATUS Status;
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if (Wrapper->WrapId == GPP_WRAP_ID) {
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Status = PcieOnGetGppConfigurationValue (ConfigurationSignature, ConfigurationValue);
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} else {
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Status = AGESA_ERROR;
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}
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return Status;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Get max link speed capability supported by this port
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*
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*
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*
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* @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX
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* @param[in] Engine Pointer to engine config descriptor
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* @param[in] Pcie Pointer to global PCIe configuration
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* @retval PcieGen1/PcieGen2 Max supported link gen capability
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*/
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PCIE_LINK_SPEED_CAP
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PcieFmGetLinkSpeedCap (
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IN UINT32 Flags,
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IN PCIe_ENGINE_CONFIG *Engine,
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IN PCIe_PLATFORM_CONFIG *Pcie
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)
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{
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PCIE_LINK_SPEED_CAP LinkSpeedCapability;
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ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen);
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LinkSpeedCapability = PcieGen2;
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if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) {
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Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability;
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}
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if (Pcie->PsppPolicy == PsppPowerSaving) {
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LinkSpeedCapability = PcieGen1;
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}
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if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) {
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LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability;
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}
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if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) {
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if (Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
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LinkSpeedCapability = PcieGen1;
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}
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}
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return LinkSpeedCapability;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Various initialization needed prior topology and configuration initialization
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*
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*
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*
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* @param[in] Pcie Pointer to global PCIe configuration
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*
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*/
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VOID
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PcieFmPreInit (
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IN PCIe_PLATFORM_CONFIG *Pcie
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)
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{
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UINT32 Index;
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PCIe_SILICON_CONFIG *Silicon;
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PCIE_LINK_SPEED_CAP GlobalCapability;
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F14_PCIe_WRAPPER_CONFIG *F14PcieWrapper;
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Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]);
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F14PcieWrapper = &((F14_COMPLEX_CONFIG*) Silicon)->FmGppWrapper ;
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GlobalCapability = PcieUtilGlobalGenCapability (
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PCIE_PORT_GEN_CAP_MAX | PCIE_GLOBAL_GEN_CAP_ALL_PORTS,
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Pcie
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);
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if ((GlobalCapability == PcieGen1) && (F14PcieWrapper->NativeGen1Support == TRUE)) {
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PcieFmExecuteNativeGen1Reconfig (Pcie);
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}
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Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]);
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for (Index = 0; Index < ARRAY_SIZE(PcieInitTable); Index++) {
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PcieSiliconRegisterRMW (
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Silicon,
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PcieInitTable[Index].Reg,
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PcieInitTable[Index].Mask,
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PcieInitTable[Index].Data,
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FALSE,
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|
Pcie
|
|
);
|
|
}
|
|
|
|
// Set PCIe SSID.
|
|
PcieSiliconRegisterRMW (
|
|
Silicon,
|
|
WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS),
|
|
D0F0xE4_WRAP_8002_SubsystemVendorID_MASK | D0F0xE4_WRAP_8002_SubsystemID_MASK,
|
|
UserOptions.CfgGnbPcieSSID,
|
|
FALSE,
|
|
Pcie
|
|
);
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------------------*/
|
|
/**
|
|
* Check if engine can be remapped to Device/function number requested by user
|
|
* defined engine descriptor
|
|
*
|
|
* Function only called if requested device/function does not much native device/function
|
|
*
|
|
* @param[in] PortDescriptor Pointer to user defined engine descriptor
|
|
* @param[in] Engine Pointer engine configuration
|
|
* @retval TRUE Descriptor can be mapped to engine
|
|
* @retval FALSE Descriptor can NOT be mapped to engine
|
|
*/
|
|
|
|
BOOLEAN
|
|
PcieFmCheckPortPciDeviceMapping (
|
|
IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
|
|
IN PCIe_ENGINE_CONFIG *Engine
|
|
)
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------------------*/
|
|
/**
|
|
* Get core configuration string
|
|
*
|
|
* Debug function for logging configuration
|
|
*
|
|
* @param[in] Wrapper Pointer to internal configuration data area
|
|
* @param[in] ConfigurationValue Configuration value
|
|
* @retval Configuration string
|
|
*/
|
|
|
|
CONST CHAR8*
|
|
PcieFmDebugGetCoreConfigurationString (
|
|
IN PCIe_WRAPPER_CONFIG *Wrapper,
|
|
IN UINT8 ConfigurationValue
|
|
)
|
|
{
|
|
switch (ConfigurationValue) {
|
|
case 4:
|
|
return (CONST CHAR8*)"1x4, 4x1";
|
|
case 3:
|
|
return (CONST CHAR8*)"1x4, 1x2, 2x1";
|
|
case 2:
|
|
return (CONST CHAR8*)"1x4, 2x2";
|
|
case 1:
|
|
return (CONST CHAR8*)"1x4, 1x4";
|
|
default:
|
|
break;
|
|
}
|
|
return (CONST CHAR8*)" !!! Something Wrong !!!";
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------------------*/
|
|
/**
|
|
* Get wrapper name
|
|
*
|
|
* Debug function for logging wrapper name
|
|
*
|
|
* @param[in] Wrapper Pointer to internal configuration data area
|
|
* @retval Wrapper Name string
|
|
*/
|
|
|
|
CONST CHAR8*
|
|
PcieFmDebugGetWrapperNameString (
|
|
IN PCIe_WRAPPER_CONFIG *Wrapper
|
|
)
|
|
{
|
|
switch (Wrapper->WrapId) {
|
|
case GPP_WRAP_ID:
|
|
return (CONST CHAR8*)"GPPSB";
|
|
case DDI_WRAP_ID:
|
|
return (CONST CHAR8*)"Virtual DDI";
|
|
default:
|
|
break;
|
|
}
|
|
return (CONST CHAR8*)" !!! Something Wrong !!!";
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------------------*/
|
|
/**
|
|
* Get register address name
|
|
*
|
|
* Debug function for logging register trace
|
|
*
|
|
* @param[in] AddressFrame Address Frame
|
|
* @retval Register address name
|
|
*/
|
|
CONST CHAR8*
|
|
PcieFmDebugGetHostRegAddressSpaceString (
|
|
IN UINT16 AddressFrame
|
|
)
|
|
{
|
|
switch (AddressFrame) {
|
|
case 0x130:
|
|
return (CONST CHAR8*)"GPP WRAP";
|
|
case 0x110:
|
|
return (CONST CHAR8*)"GPP PIF0";
|
|
case 0x120:
|
|
return (CONST CHAR8*)"GPP PHY0";
|
|
case 0x101:
|
|
return (CONST CHAR8*)"GPP CORE";
|
|
default:
|
|
break;
|
|
}
|
|
return (CONST CHAR8*)" !!! Something Wrong !!!";
|
|
}
|
|
|
|
|
|
/*----------------------------------------------------------------------------------------*/
|
|
/**
|
|
* Execute/clean up reconfiguration for Gen 1 native mode
|
|
*
|
|
*
|
|
*
|
|
* @param[in] Pcie Pointer to global PCIe configuration
|
|
*/
|
|
VOID
|
|
PcieFmExecuteNativeGen1Reconfig (
|
|
IN PCIe_PLATFORM_CONFIG *Pcie
|
|
)
|
|
{
|
|
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmExecuteNativeGen1Reconfig Enter\n");
|
|
NbSmuServiceRequest (19, FALSE, GnbLibGetHeader (Pcie));
|
|
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmExecuteNativeGen1Reconfig Enter\n");
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------------------*/
|
|
/**
|
|
* Check if the lane can be muxed by link width requested by user
|
|
* defined engine descriptor
|
|
*
|
|
* Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16).
|
|
* Check Engine StartCoreLane could be aligned by user requested link width x2.
|
|
*
|
|
* @param[in] PortDescriptor Pointer to user defined engine descriptor
|
|
* @param[in] Engine Pointer engine configuration
|
|
* @retval TRUE Lane can be muxed
|
|
* @retval FALSE LAne can NOT be muxed
|
|
*/
|
|
|
|
BOOLEAN
|
|
PcieFmCheckPortPcieLaneCanBeMuxed (
|
|
IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
|
|
IN PCIe_ENGINE_CONFIG *Engine
|
|
)
|
|
{
|
|
UINT16 DescriptorHiLane;
|
|
UINT16 DescriptorLoLane;
|
|
UINT16 DescriptorNumberOfLanes;
|
|
PCIe_WRAPPER_CONFIG *Wrapper;
|
|
UINT16 NormalizedLoPhyLane;
|
|
BOOLEAN Result;
|
|
|
|
Result = FALSE;
|
|
Wrapper = (PCIe_WRAPPER_CONFIG *)Engine->Wrapper;
|
|
DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
|
|
DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
|
|
DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
|
|
|
|
NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane;
|
|
|
|
if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) {
|
|
Result = TRUE;
|
|
} else {
|
|
if (((Engine->Type.Port.StartCoreLane % 2) == 0) || (Engine->Type.Port.StartCoreLane == 0)) {
|
|
if (NormalizedLoPhyLane == 0) {
|
|
Result = TRUE;
|
|
} else {
|
|
if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) {
|
|
Result = TRUE;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|