819 lines
22 KiB
C
819 lines
22 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* Graphics Controller family specific service procedure
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*
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*
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: GNB
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* @e \$Revision: 48498 $ @e \$Date: 2011-03-09 12:44:53 -0700 (Wed, 09 Mar 2011) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2011, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* ***************************************************************************
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*
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*/
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include "Ids.h"
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#include "Gnb.h"
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#include "GnbFuseTable.h"
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#include "GnbPcie.h"
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#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
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#include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1)
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#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
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#include "NbConfigData.h"
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#include "OptionGnb.h"
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#include "NbLclkDpm.h"
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#include "NbFamilyServices.h"
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#include "NbPowerMgmt.h"
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#include "GfxLib.h"
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#include "GnbRegistersON.h"
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#include "cpuFamilyTranslation.h"
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#include "Filecode.h"
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#define FILECODE PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*----------------------------------------------------------------------------------------
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*/
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extern GNB_BUILD_OPTIONS GnbBuildOptions;
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FUSE_TABLE FuseTable;
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/*----------------------------------------------------------------------------------------
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* P R O T O T Y P E S O F L O C A L F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------*/
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/**
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* NB family specific clock gating
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*
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*
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* @param[in, out] NbClkGatingCtrl Pointer to NB_CLK_GATING_CTRL
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* @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS
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*/
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VOID
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NbFmNbClockGating (
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IN OUT VOID *NbClkGatingCtrl,
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IN AMD_CONFIG_PARAMS *StdHeader
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)
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{
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NB_CLK_GATING_CTRL *NbClkGatingCtrlPtr;
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CPU_LOGICAL_ID LogicalId;
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NbClkGatingCtrlPtr = (NB_CLK_GATING_CTRL *)NbClkGatingCtrl;
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GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
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if ((LogicalId.Revision & AMD_F14_ON_Cx) != 0) {
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NbClkGatingCtrlPtr->Smu_Sclk_Gating = FALSE;
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}
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* UnitID Clumping
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*
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*
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* @param[in] NbPciAddress
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* @param[in] StdHeader
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* @retval AGESA_STATUS
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*/
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VOID
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NbFmClumpUnitID (
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IN PCI_ADDR NbPciAddress,
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IN AMD_CONFIG_PARAMS *StdHeader
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)
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{
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return;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Get Fuse translation table
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*
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*
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* @retval pointer to fuse translation table
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*/
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FUSE_TABLE*
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NbFmGetFuseTranslationTable (
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VOID
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)
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{
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return &FuseTable;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Family specific fuse table patch
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* Is's correct behavior if we would have 4 states, it would be
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* PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 5
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* PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 6
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* PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 7
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* If we would have 4 states it would be
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* PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 4
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* PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 5
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* PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 6
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* PP_FUSE_ARRAY->LclkDpmDid[3] - Goes to State 7
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*
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* @param[in] PpFuseArray Pointer to PP_FUSE_ARRAY
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* @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS
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*/
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VOID
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NbFmFuseAdjustFuseTablePatch (
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IN OUT PP_FUSE_ARRAY *PpFuseArray,
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IN AMD_CONFIG_PARAMS *StdHeader
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)
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{
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UINT8 LclkDpmMode;
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UINT8 SwSatateIndex;
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UINT8 MaxSclkIndex;
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UINT8 DpmStateIndex;
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UINT8 CurrentSclkDpmDid;
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CPU_LOGICAL_ID LogicalId;
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LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled;
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GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
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if ((LogicalId.Revision & (AMD_F14_ON_A0 | AMD_F14_ON_A1)) != 0) {
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LclkDpmMode = LclkDpmDisabled;
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}
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IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader);
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//For all CPU rev LclkDpmValid[3] = 0
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PpFuseArray->LclkDpmValid[3] = 0;
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PpFuseArray->LclkDpmVid[3] = 0;
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PpFuseArray->LclkDpmDid[3] = 0;
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// For LCLKDPM set LclkDpmVid[0] = 0, no matter if LCLK DMP enable or disable.
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PpFuseArray->LclkDpmVid[0] = 0;
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if (LclkDpmMode != LclkDpmRcActivity) {
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//If LCLK DPM disable (LclkDpmMode != LclkDpmRcActivity)
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// - LclkDpmDid[1,2] = LclkDpmDid [0], LclkDpmVid[1,2] = LclkDpmVid[0]
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// - Execute LCLK DPM init
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PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0];
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PpFuseArray->LclkDpmVid[2] = PpFuseArray->LclkDpmVid[0];
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PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0];
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PpFuseArray->LclkDpmDid[2] = PpFuseArray->LclkDpmDid[0];
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IDS_HDT_CONSOLE (NB_MISC, " F14 LCLK DPM Mode Disable -- use DPM0 fusing\n");
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} else {
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// If LCLK DPM enabled
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// - use fused values for LclkDpmDid[0,1,2] and appropriate voltage
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// - Execute LCLK DPM init
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PpFuseArray->LclkDpmVid[2] = PpFuseArray->PcieGen2Vid;
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if (GfxLibIsControllerPresent (StdHeader)) {
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//VID index = VID index associated with highest SCLK DPM state in the Powerplay state where Label_Performance=1 // This would ignore the UVD case (where Label_Performance would be 0).
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for (SwSatateIndex = 0 ; SwSatateIndex < PP_FUSE_MAX_NUM_SW_STATE; SwSatateIndex++) {
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if (PpFuseArray->PolicyLabel[SwSatateIndex] == POLICY_LABEL_PERFORMANCE) {
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break;
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}
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}
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MaxSclkIndex = 0;
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CurrentSclkDpmDid = 0xff;
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ASSERT (PpFuseArray->SclkDpmValid[SwSatateIndex] != 0);
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for (DpmStateIndex = 0; DpmStateIndex < PP_FUSE_MAX_NUM_DPM_STATE; DpmStateIndex++) {
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if ((PpFuseArray->SclkDpmValid[SwSatateIndex] & (1 << DpmStateIndex)) != 0) {
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if (PpFuseArray->SclkDpmDid[DpmStateIndex] < CurrentSclkDpmDid) {
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CurrentSclkDpmDid = PpFuseArray->SclkDpmDid[DpmStateIndex];
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MaxSclkIndex = DpmStateIndex;
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}
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}
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}
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PpFuseArray->LclkDpmVid[1] = PpFuseArray->SclkDpmVid[MaxSclkIndex];
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} else {
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PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0];
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PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0];
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}
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// - use fused values for LclkDpmDid[0,1,2] and appropriate voltage
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//Keep using actual fusing
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IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actual fusing.\n");
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}
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//Patch SclkThermDid to 175Mhz if not fused
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if (PpFuseArray->SclkThermDid == 0) {
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PpFuseArray->SclkThermDid = GfxLibCalculateDid (175 * 100, GfxLibGetMainPllFreq (StdHeader) * 100);
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}
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}
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/*----------------------------------------------------------------------------------------
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* FUSE translation table
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*----------------------------------------------------------------------------------------
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*/
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FUSE_REGISTER_ENTRY FCRxFE00_600E_TABLE [] = {
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{
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FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET,
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FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, MainPllId)
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},
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{
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FCRxFE00_600E_WrCkDid_OFFSET,
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FCRxFE00_600E_WrCkDid_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, WrCkDid)
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}
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};
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FUSE_REGISTER_ENTRY FCRxFE00_70A2_TABLE [] = {
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{
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FCRxFE00_70A2_PPlayTableRev_OFFSET,
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FCRxFE00_70A2_PPlayTableRev_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, PPlayTableRev)
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},
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{
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FCRxFE00_70A2_SclkThermDid_OFFSET,
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FCRxFE00_70A2_SclkThermDid_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkThermDid)
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},
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{
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FCRxFE00_70A2_PcieGen2Vid_OFFSET,
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FCRxFE00_70A2_PcieGen2Vid_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, PcieGen2Vid)
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}
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};
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FUSE_REGISTER_ENTRY FCRxFE00_70A4_TABLE [] = {
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{
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FCRxFE00_70A4_SclkDpmVid0_OFFSET,
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FCRxFE00_70A4_SclkDpmVid0_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0])
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},
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{
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FCRxFE00_70A4_SclkDpmVid1_OFFSET,
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FCRxFE00_70A4_SclkDpmVid1_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1])
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},
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{
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FCRxFE00_70A4_SclkDpmVid2_OFFSET,
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FCRxFE00_70A4_SclkDpmVid2_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2])
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},
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{
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FCRxFE00_70A4_SclkDpmVid3_OFFSET,
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FCRxFE00_70A4_SclkDpmVid3_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3])
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},
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{
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FCRxFE00_70A4_SclkDpmVid4_OFFSET,
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FCRxFE00_70A4_SclkDpmVid4_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4])
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},
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};
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FUSE_REGISTER_ENTRY FCRxFE00_70A5_TABLE [] = {
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{
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FCRxFE00_70A5_SclkDpmDid0_OFFSET,
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FCRxFE00_70A5_SclkDpmDid0_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0])
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},
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{
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FCRxFE00_70A5_SclkDpmDid1_OFFSET,
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FCRxFE00_70A5_SclkDpmDid1_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1])
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},
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{
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FCRxFE00_70A5_SclkDpmDid2_OFFSET,
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FCRxFE00_70A5_SclkDpmDid2_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2])
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}
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};
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FUSE_REGISTER_ENTRY FCRxFE00_70A8_TABLE [] = {
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{
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FCRxFE00_70A8_SclkDpmDid3_OFFSET,
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FCRxFE00_70A8_SclkDpmDid3_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3])
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},
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{
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FCRxFE00_70A8_SclkDpmDid4_OFFSET,
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FCRxFE00_70A8_SclkDpmDid4_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4])
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}
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};
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FUSE_REGISTER_ENTRY FCRxFE00_70AA_TABLE [] = {
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{
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FCRxFE00_70AA_SclkDpmCacBase_OFFSET,
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FCRxFE00_70AA_SclkDpmCacBase_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmCac[4])
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}
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};
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FUSE_REGISTER_ENTRY FCRxFE00_70AE_TABLE [] = {
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{
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FCRxFE00_70AE_DispClkDid0_OFFSET,
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FCRxFE00_70AE_DispClkDid0_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[0])
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},
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{
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FCRxFE00_70AE_DispClkDid1_OFFSET,
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FCRxFE00_70AE_DispClkDid1_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[1])
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},
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{
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FCRxFE00_70AE_DispClkDid2_OFFSET,
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FCRxFE00_70AE_DispClkDid2_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[2])
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},
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{
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FCRxFE00_70AE_DispClkDid3_OFFSET,
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FCRxFE00_70AE_DispClkDid3_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[3])
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}
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};
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FUSE_REGISTER_ENTRY FCRxFE00_70B1_TABLE [] = {
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{
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FCRxFE00_70B1_LclkDpmDid0_OFFSET,
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FCRxFE00_70B1_LclkDpmDid0_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0])
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},
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{
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FCRxFE00_70B1_LclkDpmDid1_OFFSET,
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FCRxFE00_70B1_LclkDpmDid1_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1])
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},
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{
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FCRxFE00_70B1_LclkDpmDid2_OFFSET,
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FCRxFE00_70B1_LclkDpmDid2_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2])
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}
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};
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FUSE_REGISTER_ENTRY FCRxFE00_70B4_TABLE [] = {
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{
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FCRxFE00_70B4_LclkDpmDid3_OFFSET,
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FCRxFE00_70B4_LclkDpmDid3_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3])
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},
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{
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FCRxFE00_70B4_LclkDpmValid0_OFFSET,
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FCRxFE00_70B4_LclkDpmValid0_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0])
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},
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{
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FCRxFE00_70B4_LclkDpmValid1_OFFSET,
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FCRxFE00_70B4_LclkDpmValid1_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1])
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},
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{
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FCRxFE00_70B4_LclkDpmValid2_OFFSET,
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FCRxFE00_70B4_LclkDpmValid2_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2])
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},
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{
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FCRxFE00_70B4_LclkDpmValid3_OFFSET,
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FCRxFE00_70B4_LclkDpmValid3_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3])
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}
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};
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FUSE_REGISTER_ENTRY FCRxFE00_70B5_TABLE [] = {
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{
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FCRxFE00_70B5_DclkDid0_OFFSET,
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FCRxFE00_70B5_DclkDid0_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[0])
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},
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{
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FCRxFE00_70B5_DclkDid1_OFFSET,
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FCRxFE00_70B5_DclkDid1_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[1])
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},
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{
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FCRxFE00_70B5_DclkDid2_OFFSET,
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FCRxFE00_70B5_DclkDid2_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[2])
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}
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};
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FUSE_REGISTER_ENTRY FCRxFE00_70B8_TABLE [] = {
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|
{
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FCRxFE00_70B8_DclkDid3_OFFSET,
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FCRxFE00_70B8_DclkDid3_WIDTH,
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(UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[3])
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}
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};
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|
|
FUSE_REGISTER_ENTRY FCRxFE00_70B9_TABLE [] = {
|
|
{
|
|
FCRxFE00_70B9_VclkDid0_OFFSET,
|
|
FCRxFE00_70B9_VclkDid0_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[0])
|
|
},
|
|
{
|
|
FCRxFE00_70B9_VclkDid1_OFFSET,
|
|
FCRxFE00_70B9_VclkDid1_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[1])
|
|
},
|
|
{
|
|
FCRxFE00_70B9_VclkDid2_OFFSET,
|
|
FCRxFE00_70B9_VclkDid2_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[2])
|
|
},
|
|
{
|
|
FCRxFE00_70B9_VclkDid3_OFFSET,
|
|
FCRxFE00_70B9_VclkDid3_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[3])
|
|
}
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70BC_TABLE [] = {
|
|
{
|
|
FCRxFE00_70BC_SclkDpmValid0_OFFSET,
|
|
FCRxFE00_70BC_SclkDpmValid0_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0])
|
|
},
|
|
{
|
|
FCRxFE00_70BC_SclkDpmValid1_OFFSET,
|
|
FCRxFE00_70BC_SclkDpmValid1_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1])
|
|
},
|
|
{
|
|
FCRxFE00_70BC_SclkDpmValid2_OFFSET,
|
|
FCRxFE00_70BC_SclkDpmValid2_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2])
|
|
},
|
|
{
|
|
FCRxFE00_70BC_SclkDpmValid3_OFFSET,
|
|
FCRxFE00_70BC_SclkDpmValid3_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3])
|
|
},
|
|
{
|
|
FCRxFE00_70BC_SclkDpmValid4_OFFSET,
|
|
FCRxFE00_70BC_SclkDpmValid4_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4])
|
|
}
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70BF_TABLE [] = {
|
|
{
|
|
FCRxFE00_70BF_SclkDpmValid5_OFFSET,
|
|
FCRxFE00_70BF_SclkDpmValid5_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5])
|
|
}
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70C0_TABLE [] = {
|
|
{
|
|
FCRxFE00_70C0_PolicyLabel0_OFFSET,
|
|
FCRxFE00_70C0_PolicyLabel0_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[0])
|
|
},
|
|
{
|
|
FCRxFE00_70C0_PolicyLabel1_OFFSET,
|
|
FCRxFE00_70C0_PolicyLabel1_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[1])
|
|
},
|
|
{
|
|
FCRxFE00_70C0_PolicyLabel2_OFFSET,
|
|
FCRxFE00_70C0_PolicyLabel2_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[2])
|
|
},
|
|
{
|
|
FCRxFE00_70C0_PolicyLabel3_OFFSET,
|
|
FCRxFE00_70C0_PolicyLabel3_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[3])
|
|
},
|
|
{
|
|
FCRxFE00_70C0_PolicyLabel4_OFFSET,
|
|
FCRxFE00_70C0_PolicyLabel4_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[4])
|
|
},
|
|
{
|
|
FCRxFE00_70C0_PolicyLabel5_OFFSET,
|
|
FCRxFE00_70C0_PolicyLabel5_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[5])
|
|
}
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70C1_TABLE [] = {
|
|
{
|
|
FCRxFE00_70C1_PolicyFlags0_OFFSET,
|
|
FCRxFE00_70C1_PolicyFlags0_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[0])
|
|
},
|
|
{
|
|
FCRxFE00_70C1_PolicyFlags1_OFFSET,
|
|
FCRxFE00_70C1_PolicyFlags1_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[1])
|
|
},
|
|
{
|
|
FCRxFE00_70C1_PolicyFlags2_OFFSET,
|
|
FCRxFE00_70C1_PolicyFlags2_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[2])
|
|
}
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70C4_TABLE [] = {
|
|
{
|
|
FCRxFE00_70C4_PolicyFlags3_OFFSET,
|
|
FCRxFE00_70C4_PolicyFlags3_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[3])
|
|
},
|
|
{
|
|
FCRxFE00_70C4_PolicyFlags4_OFFSET,
|
|
FCRxFE00_70C4_PolicyFlags4_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[4])
|
|
},
|
|
{
|
|
FCRxFE00_70C4_PolicyFlags5_OFFSET,
|
|
FCRxFE00_70C4_PolicyFlags5_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[5])
|
|
}
|
|
};
|
|
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70C7_TABLE [] = {
|
|
{
|
|
FCRxFE00_70C7_DclkVclkSel0_OFFSET,
|
|
FCRxFE00_70C7_DclkVclkSel0_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0])
|
|
},
|
|
{
|
|
FCRxFE00_70C7_DclkVclkSel1_OFFSET,
|
|
FCRxFE00_70C7_DclkVclkSel1_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1])
|
|
},
|
|
{
|
|
FCRxFE00_70C7_DclkVclkSel2_OFFSET,
|
|
FCRxFE00_70C7_DclkVclkSel2_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2])
|
|
},
|
|
{
|
|
FCRxFE00_70C7_DclkVclkSel3_OFFSET,
|
|
FCRxFE00_70C7_DclkVclkSel3_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3])
|
|
},
|
|
|
|
{
|
|
FCRxFE00_70C7_DclkVclkSel4_OFFSET,
|
|
FCRxFE00_70C7_DclkVclkSel4_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4])
|
|
},
|
|
{
|
|
FCRxFE00_70C7_DclkVclkSel5_OFFSET,
|
|
FCRxFE00_70C7_DclkVclkSel5_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5])
|
|
},
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70C8_TABLE [] = {
|
|
{
|
|
FCRxFE00_70C8_GpuBoostCap_OFFSET,
|
|
FCRxFE00_70C8_GpuBoostCap_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, GpuBoostCap)
|
|
},
|
|
{
|
|
FCRxFE00_70C8_SclkDpmVid5_OFFSET,
|
|
FCRxFE00_70C8_SclkDpmVid5_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[5])
|
|
},
|
|
{
|
|
FCRxFE00_70C8_SclkDpmDid5_OFFSET,
|
|
FCRxFE00_70C8_SclkDpmDid5_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[5])
|
|
},
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70C9_TABLE [] = {
|
|
{
|
|
FCRxFE00_70C9_SclkDpmTdpLimit0_OFFSET,
|
|
FCRxFE00_70C9_SclkDpmTdpLimit0_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[0])
|
|
},
|
|
{
|
|
FCRxFE00_70C9_SclkDpmTdpLimit1_OFFSET,
|
|
FCRxFE00_70C9_SclkDpmTdpLimit1_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[1])
|
|
}
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70CC_TABLE [] = {
|
|
{
|
|
FCRxFE00_70CC_SclkDpmTdpLimit2_OFFSET,
|
|
FCRxFE00_70CC_SclkDpmTdpLimit2_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[2])
|
|
},
|
|
{
|
|
FCRxFE00_70CC_SclkDpmTdpLimit3_OFFSET,
|
|
FCRxFE00_70CC_SclkDpmTdpLimit3_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[3])
|
|
}
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70CF_TABLE [] = {
|
|
{
|
|
FCRxFE00_70CF_SclkDpmTdpLimit4_OFFSET,
|
|
FCRxFE00_70CF_SclkDpmTdpLimit4_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[4])
|
|
},
|
|
{
|
|
FCRxFE00_70CF_SclkDpmTdpLimit5_OFFSET,
|
|
FCRxFE00_70CF_SclkDpmTdpLimit5_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[5])
|
|
}
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70D2_TABLE [] = {
|
|
{
|
|
FCRxFE00_70D2_SclkDpmTdpLimitPG_OFFSET,
|
|
FCRxFE00_70D2_SclkDpmTdpLimitPG_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimitPG)
|
|
}
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70D4_TABLE [] = {
|
|
{
|
|
FCRxFE00_70D4_SclkDpmBoostMargin_OFFSET,
|
|
FCRxFE00_70D4_SclkDpmBoostMargin_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmBoostMargin)
|
|
}
|
|
};
|
|
|
|
FUSE_REGISTER_ENTRY FCRxFE00_70D7_TABLE [] = {
|
|
{
|
|
FCRxFE00_70D7_SclkDpmThrottleMargin_OFFSET,
|
|
FCRxFE00_70D7_SclkDpmThrottleMargin_WIDTH,
|
|
(UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmThrottleMargin)
|
|
}
|
|
};
|
|
|
|
FUSE_TABLE_ENTRY FuseRegisterTable [] = {
|
|
{
|
|
FCRxFE00_70A2_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70A2_TABLE),
|
|
FCRxFE00_70A2_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70A4_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70A4_TABLE),
|
|
FCRxFE00_70A4_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70A5_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70A5_TABLE),
|
|
FCRxFE00_70A5_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70A8_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70A8_TABLE),
|
|
FCRxFE00_70A8_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_600E_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_600E_TABLE),
|
|
FCRxFE00_600E_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70AA_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70AA_TABLE),
|
|
FCRxFE00_70AA_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70AE_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70AE_TABLE),
|
|
FCRxFE00_70AE_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70B1_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70B1_TABLE),
|
|
FCRxFE00_70B1_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70B4_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70B4_TABLE),
|
|
FCRxFE00_70B4_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70B5_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70B5_TABLE),
|
|
FCRxFE00_70B5_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70B8_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70B8_TABLE),
|
|
FCRxFE00_70B8_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70B9_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70B9_TABLE),
|
|
FCRxFE00_70B9_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70BC_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70BC_TABLE),
|
|
FCRxFE00_70BC_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70BF_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70BF_TABLE),
|
|
FCRxFE00_70BF_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70C0_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70C0_TABLE),
|
|
FCRxFE00_70C0_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70C1_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70C1_TABLE),
|
|
FCRxFE00_70C1_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70C4_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70C4_TABLE),
|
|
FCRxFE00_70C4_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70C7_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70C7_TABLE),
|
|
FCRxFE00_70C7_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70C8_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70C8_TABLE),
|
|
FCRxFE00_70C8_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70C9_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70C9_TABLE),
|
|
FCRxFE00_70C9_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70CC_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70CC_TABLE),
|
|
FCRxFE00_70CC_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70CF_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70CF_TABLE),
|
|
FCRxFE00_70CF_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70D2_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70D2_TABLE),
|
|
FCRxFE00_70D2_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70D4_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70D4_TABLE),
|
|
FCRxFE00_70D4_TABLE
|
|
},
|
|
{
|
|
FCRxFE00_70D7_ADDRESS,
|
|
ARRAY_SIZE(FCRxFE00_70D7_TABLE),
|
|
FCRxFE00_70D7_TABLE
|
|
},
|
|
};
|
|
|
|
FUSE_TABLE FuseTable = {
|
|
ARRAY_SIZE(FuseRegisterTable),
|
|
FuseRegisterTable
|
|
};
|