640 lines
19 KiB
C
640 lines
19 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* Graphics Controller family specific service procedure
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*
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*
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: GNB
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* @e \$Revision: 48507 $ @e \$Date: 2011-03-09 13:25:11 -0700 (Wed, 09 Mar 2011) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2011, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* ***************************************************************************
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*
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*/
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include "Ids.h"
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#include "heapManager.h"
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#include "GeneralServices.h"
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#include "Gnb.h"
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#include "GnbPcie.h"
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#include "GnbGfx.h"
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#include "GnbRegistersON.h"
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#include "GfxIntegratedInfoTableInit.h"
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#include "GfxRegisterAcc.h"
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#include "GfxLib.h"
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#include "GnbFuseTable.h"
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#include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1)
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#include "GnbCommonLib.h"
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#include "GnbCommonLib.h"
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#include "GnbGfxFamServices.h"
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#include "GfxFamilyServices.h"
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#include "F14NbPowerGate.h"
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#include "cpuFamilyTranslation.h"
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#include "Filecode.h"
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#define FILECODE PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* P R O T O T Y P E S O F L O C A L F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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UINT8 NumberOfChannels = 1;
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UINT8 DdiLaneConfigArray [][4] = {
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{8, 11, 0, 0},
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{12, 15, 1, 1},
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{11, 8, 0, 0},
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{15, 12, 1, 1},
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{16, 19, 6, 6},
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{19, 16, 6, 6}
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};
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/*----------------------------------------------------------------------------------------*/
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/**
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* Initialize display path for given engine
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*
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*
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*
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* @param[in] Engine Engine configuration info
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* @param[out] DisplayPathList Display path list
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* @param[in] Gfx Pointer to global GFX configuration
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*/
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AGESA_STATUS
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GfxFmMapEngineToDisplayPath (
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IN PCIe_ENGINE_CONFIG *Engine,
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OUT EXT_DISPLAY_PATH *DisplayPathList,
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IN GFX_PLATFORM_CONFIG *Gfx
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)
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{
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AGESA_STATUS Status;
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UINT8 PrimaryDisplayPathId;
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UINT8 SecondaryDisplayPathId;
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UINTN DisplayPathIndex;
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UINT32 D18F3x1FC;
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PrimaryDisplayPathId = 0xff;
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SecondaryDisplayPathId = 0xff;
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for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArray) / 4); DisplayPathIndex++) {
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if (DdiLaneConfigArray[DisplayPathIndex][0] == Engine->EngineData.StartLane &&
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DdiLaneConfigArray[DisplayPathIndex][1] == Engine->EngineData.EndLane) {
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PrimaryDisplayPathId = DdiLaneConfigArray[DisplayPathIndex][2];
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SecondaryDisplayPathId = DdiLaneConfigArray[DisplayPathIndex][3];
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break;
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}
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}
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if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI ||
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(Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds && PrimaryDisplayPathId != 0)) {
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// Display config invalid for ON
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PrimaryDisplayPathId = 0xff;
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}
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GnbLibPciRead (
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MAKE_SBDFO ( 0, 0, 0x18, 3, 0x1FC),
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AccessWidth32,
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&D18F3x1FC,
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GnbLibGetHeader (Gfx)
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);
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if ((D18F3x1FC & BIT4) == BIT4) {
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if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect ||
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(Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds)) {
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PrimaryDisplayPathId = 0xff;
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}
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}
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if (PrimaryDisplayPathId != 0xff) {
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ASSERT (Engine->Type.Ddi.DdiData.AuxIndex <= Aux3);
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IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId);
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Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE;
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if (Engine->Type.Ddi.DdiData.AuxIndex == Aux3) {
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Engine->Type.Ddi.DdiData.AuxIndex = 7;
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}
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GfxIntegratedCopyDisplayInfo (
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Engine,
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&DisplayPathList[PrimaryDisplayPathId],
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(PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL,
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Gfx
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);
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if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) {
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LibAmdMemCopy (&DisplayPathList[6], &DisplayPathList[PrimaryDisplayPathId], sizeof (EXT_DISPLAY_PATH), GnbLibGetHeader (Gfx));
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DisplayPathList[6].usDeviceACPIEnum = 0x100;
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DisplayPathList[6].usDeviceTag = ATOM_DEVICE_CRT1_SUPPORT;
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}
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Status = AGESA_SUCCESS;
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} else {
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IDS_HDT_CONSOLE (GFX_MISC, " ERROR!!! Map DDI lanes %d - %d to display path failed\n",
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Engine->EngineData.StartLane,
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Engine->EngineData.EndLane
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);
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PutEventLog (
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AGESA_ERROR,
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GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION,
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Engine->EngineData.StartLane,
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Engine->EngineData.EndLane,
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0,
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0,
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GnbLibGetHeader (Gfx)
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);
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Status = AGESA_ERROR;
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}
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return Status;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Family specific integrated info table init
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*
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*
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* @param[in] IntegratedInfoTable Integrated info table pointer
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* @param[in] Gfx Gfx configuration info
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*/
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VOID
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GfxFmIntegratedInfoTableInit (
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IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
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IN GFX_PLATFORM_CONFIG *Gfx
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)
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{
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PP_FUSE_ARRAY *PpFuseArray;
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D18F4x15C_STRUCT D18F4x15C;
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PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
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ASSERT (PpFuseArray != NULL);
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if (PpFuseArray != NULL) {
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if (PpFuseArray->GpuBoostCap == 1) {
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GnbLibPciRead (
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MAKE_SBDFO ( 0, 0, 0x18, 4, D18F4x15C_ADDRESS),
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AccessWidth32,
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&D18F4x15C.Value,
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GnbLibGetHeader (Gfx)
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);
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D18F4x15C.Field.BoostSrc = 1;
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GnbLibPciWrite (
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MAKE_SBDFO ( 0, 0, 0x18, 4, D18F4x15C_ADDRESS),
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AccessS3SaveWidth32,
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&D18F4x15C.Value,
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GnbLibGetHeader (Gfx)
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);
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}
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}
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IntegratedInfoTable->ulDDR_DLL_PowerUpTime = 2380;
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IntegratedInfoTable->ulDDR_PLL_PowerUpTime = 30000;
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IntegratedInfoTable->ulGMCRestoreResetTime = F14NbPowerGateGmcRestoreLatency (GnbLibGetHeader (Gfx));
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Family specific address swizzle settings.
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*
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*
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* @param[in] Gfx Gfx configuration info
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*/
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VOID
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GfxFmGmcAddressSwizzel (
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IN GFX_PLATFORM_CONFIG *Gfx
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)
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{
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GMMx2864_STRUCT GMMx2864;
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GMMx2864.Value = GmmRegisterRead (GMMx2864_ADDRESS, Gfx);
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if (GMMx2864.Value == 0) {
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GMMx2864.Value = 0x32100876;
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GmmRegisterWrite (
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GMMx2864_ADDRESS,
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GMMx2864.Value,
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TRUE,
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Gfx
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);
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}
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Initialize Allow_Nb_Pstate High
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*
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*
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*
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* @param[in] Gfx Graphics configuration
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*/
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VOID
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GfxFmGmcAllowPstateHigh (
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IN GFX_PLATFORM_CONFIG *Gfx
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)
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{
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GMMxCAC_STRUCT GMMxCAC;
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GMMxCCC_STRUCT GMMxCCC;
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GMMx6B30_STRUCT GMMx6B30;
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GMMx7730_STRUCT GMMx7730;
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CPU_LOGICAL_ID LogicalId;
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GetLogicalIdOfCurrentCore (&LogicalId, GnbLibGetHeader (Gfx));
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//
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//A workaround for F14 A0. This has be fixed in the future vesions.
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//
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if ((LogicalId.Revision & AMD_F14_ON_A0) != 0) {
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//For PCIE Enhanced Mode
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GMMx6B30.Value = GmmRegisterRead (GMMx6B30_ADDRESS, Gfx);
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GMMx7730.Value = GmmRegisterRead (GMMx7730_ADDRESS, Gfx);
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GMMx6B30.Field.DcAllowNbPstatesForceOne = 1;
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GMMx7730.Field.DcAllowNbPstatesForceOne = 1;
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GmmRegisterWrite (GMMx6B30_ADDRESS, GMMx6B30.Value, TRUE, Gfx);
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GmmRegisterWrite (GMMx7730_ADDRESS, GMMx7730.Value, TRUE, Gfx);
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//For Legacy mode
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GMMxCAC.Value = GmmRegisterRead (GMMxCAC_ADDRESS, Gfx);
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GMMxCCC.Value = GmmRegisterRead (GMMxCCC_ADDRESS, Gfx);
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GMMxCAC.Field.NbPstateChangeForceOn = 1;
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GMMxCCC.Field.NbPstateChangeForceOn = 1;
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GmmRegisterWrite (GMMxCAC_ADDRESS, GMMxCAC.Value, TRUE, Gfx);
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GmmRegisterWrite (GMMxCCC_ADDRESS, GMMxCCC.Value, TRUE, Gfx);
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}
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Calculate COF for DFS out of Main PLL
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*
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*
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*
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* @param[in] Did Did
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* @param[in] StdHeader Standard Configuration Header
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* @retval COF in 10khz
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*/
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UINT32
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GfxFmCalculateClock (
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IN UINT8 Did,
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IN AMD_CONFIG_PARAMS *StdHeader
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)
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{
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UINT32 MainPllFreq10kHz;
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MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100;
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return GfxLibCalculateClk (Did, MainPllFreq10kHz);
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Set idle voltage mode for GFX
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*
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*
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* @param[in] Gfx Pointer to global GFX configuration
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*/
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VOID
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GfxFmSetIdleVoltageMode (
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IN GFX_PLATFORM_CONFIG *Gfx
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)
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{
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}
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/*----------------------------------------------------------------------------------------
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* GMC Disable Clock Gating
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*----------------------------------------------------------------------------------------
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*/
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GMM_REG_ENTRY GmcDisableClockGating[] = {
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{ GMMx20C0_ADDRESS, 0x00000C80 },
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{ GMMx20B8_ADDRESS, 0x00000400 },
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{ GMMx20BC_ADDRESS, 0x00000400 },
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{ GMMx2640_ADDRESS, 0x00000400 },
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{ GMMx263C_ADDRESS, 0x00000400 },
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{ GMMx2638_ADDRESS, 0x00000400 },
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{ GMMx15C0_ADDRESS, 0x00081401 }
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};
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TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = {
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ARRAY_SIZE(GmcDisableClockGating),
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GmcDisableClockGating
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};
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/*----------------------------------------------------------------------------------------
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* GMC Enable Clock Gating
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*----------------------------------------------------------------------------------------
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*/
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GMM_REG_ENTRY GmcEnableClockGating[] = {
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{ GMMx20C0_ADDRESS, 0x00040C80 },
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{ GMMx20B8_ADDRESS, 0x00040400 },
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{ GMMx20BC_ADDRESS, 0x00040400 },
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{ GMMx2640_ADDRESS, 0x00040400 },
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{ GMMx263C_ADDRESS, 0x00040400 },
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{ GMMx2638_ADDRESS, 0x00040400 },
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{ GMMx15C0_ADDRESS, 0x000C1401 }
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};
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TABLE_INDIRECT_PTR GmcEnableClockGatingPtr = {
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ARRAY_SIZE(GmcEnableClockGating),
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GmcEnableClockGating
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};
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/*----------------------------------------------------------------------------------------
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* GMC Performance Tuning
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*----------------------------------------------------------------------------------------
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*/
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GMM_REG_ENTRY GmcPerformanceTuningTable [] = {
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{ GMMx27CC_ADDRESS, 0x00032005 },
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{ GMMx27DC_ADDRESS, 0x00734847 },
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{ GMMx27D0_ADDRESS, 0x00012008 },
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{ GMMx27E0_ADDRESS, 0x00003D3C },
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{ GMMx2784_ADDRESS, 0x00000007 },
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{ GMMx21C8_ADDRESS, 0x0000A1F1 },
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{ GMMx217C_ADDRESS, 0x0000A1F1 },
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{ GMMx2188_ADDRESS, 0x000221b1 },
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{ GMMx2814_ADDRESS, 0x00000200 },
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{ GMMx201C_ADDRESS, 0x03330003 },
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{ GMMx2020_ADDRESS, 0x70760007 },
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{ GMMx2018_ADDRESS, 0x00000050 },
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{ GMMx2014_ADDRESS, 0x00005500 },
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{ GMMx2610_ADDRESS, 0x44111222 },
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{ GMMx2618_ADDRESS, 0x00006664 },
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{ GMMx2614_ADDRESS, 0x11333111 },
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{ GMMx261C_ADDRESS, 0x00000003 },
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{ GMMx279C_ADDRESS, 0xfcfcfdfc },
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{ GMMx27A0_ADDRESS, 0xfcfcfdfc }
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};
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TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr = {
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ARRAY_SIZE(GmcPerformanceTuningTable),
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GmcPerformanceTuningTable
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};
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/*----------------------------------------------------------------------------------------
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* GMC Misc init table
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*----------------------------------------------------------------------------------------
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*/
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GMM_REG_ENTRY GmcMiscInitTable [] = {
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{ GMMx25C8_ADDRESS, 0x007F605F },
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{ GMMx25CC_ADDRESS, 0x00007F7E },
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{ GMMx20B4_ADDRESS, 0x00000000 },
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{ GMMx28C8_ADDRESS, 0x00000003 },
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{ GMMx202C_ADDRESS, 0x0003FFFF }
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};
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TABLE_INDIRECT_PTR GmcMiscInitTablePtr = {
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ARRAY_SIZE(GmcMiscInitTable),
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GmcMiscInitTable
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};
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/*----------------------------------------------------------------------------------------
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* GMC Remove blackout
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*----------------------------------------------------------------------------------------
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*/
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GMM_REG_ENTRY GmcRemoveBlackoutTable [] = {
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{ GMMx25C0_ADDRESS, 0x00000000 },
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{ GMMx20EC_ADDRESS, 0x000001FC },
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{ GMMx20D4_ADDRESS, 0x00000016 }
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};
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TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = {
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ARRAY_SIZE(GmcRemoveBlackoutTable),
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GmcRemoveBlackoutTable
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};
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/*----------------------------------------------------------------------------------------
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* GMC Register Engine Init Table
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*----------------------------------------------------------------------------------------
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*/
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GMM_REG_ENTRY GmcRegisterEngineInitTable [] = {
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{ GMMx2B8C_ADDRESS, 0x00000000 },
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{ GMMx2B90_ADDRESS, 0x001e0a07 },
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{ GMMx2B8C_ADDRESS, 0x00000020 },
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{ GMMx2B90_ADDRESS, 0x00050500 },
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{ GMMx2B8C_ADDRESS, 0x00000027 },
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{ GMMx2B90_ADDRESS, 0x0001050c },
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{ GMMx2B8C_ADDRESS, 0x0000002a },
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{ GMMx2B90_ADDRESS, 0x0001051c },
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{ GMMx2B8C_ADDRESS, 0x0000002d },
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{ GMMx2B90_ADDRESS, 0x00030534 },
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{ GMMx2B8C_ADDRESS, 0x00000032 },
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{ GMMx2B90_ADDRESS, 0x0001053e },
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{ GMMx2B8C_ADDRESS, 0x00000035 },
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{ GMMx2B90_ADDRESS, 0x00010546 },
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{ GMMx2B8C_ADDRESS, 0x00000038 },
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{ GMMx2B90_ADDRESS, 0x0002054e },
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{ GMMx2B8C_ADDRESS, 0x0000003c },
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{ GMMx2B90_ADDRESS, 0x00010557 },
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{ GMMx2B8C_ADDRESS, 0x0000003f },
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{ GMMx2B90_ADDRESS, 0x0001055f },
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{ GMMx2B8C_ADDRESS, 0x00000042 },
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{ GMMx2B90_ADDRESS, 0x00010567 },
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{ GMMx2B8C_ADDRESS, 0x00000045 },
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{ GMMx2B90_ADDRESS, 0x0001056f },
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{ GMMx2B8C_ADDRESS, 0x00000048 },
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{ GMMx2B90_ADDRESS, 0x00050572 },
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{ GMMx2B8C_ADDRESS, 0x0000004f },
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{ GMMx2B90_ADDRESS, 0x00000800 },
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{ GMMx2B8C_ADDRESS, 0x00000051 },
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|
{ GMMx2B90_ADDRESS, 0x00260801 },
|
|
{ GMMx2B8C_ADDRESS, 0x00000079 },
|
|
{ GMMx2B90_ADDRESS, 0x004b082d },
|
|
{ GMMx2B8C_ADDRESS, 0x000000c6 },
|
|
{ GMMx2B90_ADDRESS, 0x0013088d },
|
|
{ GMMx2B8C_ADDRESS, 0x000000db },
|
|
{ GMMx2B90_ADDRESS, 0x100008a1 },
|
|
{ GMMx2B90_ADDRESS, 0x00000040 },
|
|
{ GMMx2B90_ADDRESS, 0x00000040 },
|
|
{ GMMx2B8C_ADDRESS, 0x000000df },
|
|
{ GMMx2B90_ADDRESS, 0x000008a2 },
|
|
{ GMMx2B8C_ADDRESS, 0x000000e1 },
|
|
{ GMMx2B90_ADDRESS, 0x0001094d },
|
|
{ GMMx2B8C_ADDRESS, 0x000000e4 },
|
|
{ GMMx2B90_ADDRESS, 0x00000952 },
|
|
{ GMMx2B8C_ADDRESS, 0x000000e6 },
|
|
{ GMMx2B90_ADDRESS, 0x00010954 },
|
|
{ GMMx2B8C_ADDRESS, 0x000000e9 },
|
|
{ GMMx2B90_ADDRESS, 0x0009095a },
|
|
{ GMMx2B8C_ADDRESS, 0x000000f4 },
|
|
{ GMMx2B90_ADDRESS, 0x0022096e },
|
|
{ GMMx2B8C_ADDRESS, 0x00000118 },
|
|
{ GMMx2B90_ADDRESS, 0x000e0997 },
|
|
{ GMMx2B8C_ADDRESS, 0x00000128 },
|
|
{ GMMx2B90_ADDRESS, 0x100009a6 },
|
|
{ GMMx2B90_ADDRESS, 0x00000040 },
|
|
{ GMMx2B90_ADDRESS, 0x00000040 },
|
|
{ GMMx2B8C_ADDRESS, 0x0000012c },
|
|
{ GMMx2B90_ADDRESS, 0x000009a7 },
|
|
{ GMMx2B8C_ADDRESS, 0x0000012e },
|
|
{ GMMx2B90_ADDRESS, 0x002e09d7 },
|
|
{ GMMx2B8C_ADDRESS, 0x0000015e },
|
|
{ GMMx2B90_ADDRESS, 0x00170a26 },
|
|
{ GMMx2B94_ADDRESS, 0x5d976000 },
|
|
{ GMMx2B98_ADDRESS, 0x410af020 }
|
|
};
|
|
|
|
TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = {
|
|
ARRAY_SIZE(GmcRegisterEngineInitTable),
|
|
GmcRegisterEngineInitTable
|
|
};
|
|
|
|
/*----------------------------------------------------------------------------------------
|
|
* GMC Address Translation Table
|
|
*----------------------------------------------------------------------------------------
|
|
*/
|
|
// Entries for Bank 1 will be fused out
|
|
|
|
REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = {
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x40_ADDRESS),
|
|
GMMx281C_ADDRESS,
|
|
0,
|
|
31,
|
|
0,
|
|
31
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x44_ADDRESS),
|
|
GMMx2824_ADDRESS,
|
|
0,
|
|
31,
|
|
0,
|
|
31
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x48_ADDRESS),
|
|
GMMx282C_ADDRESS,
|
|
0,
|
|
31,
|
|
0,
|
|
31
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x4C_ADDRESS),
|
|
GMMx2834_ADDRESS,
|
|
0,
|
|
31,
|
|
0,
|
|
31
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x60_ADDRESS),
|
|
GMMx283C_ADDRESS,
|
|
0,
|
|
31,
|
|
0,
|
|
31
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x64_ADDRESS),
|
|
GMMx2840_ADDRESS,
|
|
0,
|
|
31,
|
|
0,
|
|
31
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x80_ADDRESS),
|
|
GMMx284C_ADDRESS,
|
|
D18F2x80_Dimm0AddrMap_OFFSET,
|
|
D18F2x80_Dimm0AddrMap_WIDTH + D18F2x80_Dimm1AddrMap_WIDTH,
|
|
GMMx284C_Dimm0AddrMap_OFFSET,
|
|
GMMx284C_Dimm0AddrMap_WIDTH + GMMx284C_Dimm1AddrMap_WIDTH
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x94_ADDRESS),
|
|
GMMx284C_ADDRESS,
|
|
D18F2x94_BankSwizzleMode_OFFSET,
|
|
D18F2x94_BankSwizzleMode_WIDTH,
|
|
GMMx284C_BankSwizzleMode_OFFSET,
|
|
GMMx284C_BankSwizzleMode_WIDTH
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2xA8_ADDRESS),
|
|
GMMx284C_ADDRESS,
|
|
D18F2xA8_BankSwap_OFFSET,
|
|
D18F2xA8_BankSwap_WIDTH,
|
|
GMMx284C_BankSwap_OFFSET,
|
|
GMMx284C_BankSwap_WIDTH
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x110_ADDRESS),
|
|
GMMx2854_ADDRESS,
|
|
0,
|
|
31,
|
|
0,
|
|
31
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x114_ADDRESS),
|
|
GMMx2858_ADDRESS,
|
|
0,
|
|
31,
|
|
0,
|
|
31
|
|
},
|
|
{
|
|
MAKE_SBDFO (0, 0, 0x18, 1, D18F1xF0_ADDRESS),
|
|
GMMx285C_ADDRESS,
|
|
0,
|
|
31,
|
|
0,
|
|
31
|
|
}
|
|
};
|
|
|
|
|
|
TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr = {
|
|
ARRAY_SIZE(CnbToGncRegisterCopyTable),
|
|
CnbToGncRegisterCopyTable
|
|
};
|
|
|