274 lines
11 KiB
C
274 lines
11 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* AMD Family_14 Power Plane Initialization
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*
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* Performs the "BIOS Requirements for Power Plane Initialization" as described
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* in the BKDG.
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: CPU/F14
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* @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
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*
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*/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2011, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* ***************************************************************************
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*
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*/
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include "Ids.h"
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#include "cpuCacheInit.h"
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#include "cpuRegisters.h"
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#include "cpuFamilyTranslation.h"
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#include "cpuServices.h"
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#include "cpuF14PowerMgmt.h"
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#include "cpuF14PowerPlane.h"
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#include "OptionFamily14hEarlySample.h"
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#include "NbSmuLib.h"
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#include "GnbRegistersON.h"
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#include "Filecode.h"
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#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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extern F14_ES_CORE_SUPPORT F14EarlySampleCoreSupport;
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// Register encodings for D18F3xD8[VSRampSlamTime]
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STATIC CONST UINT32 ROMDATA F14VSRampSlamWaitTimes[8] =
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{
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625, // 000b: 6.25us
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500, // 001b: 5.00us
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417, // 010b: 4.17us
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313, // 011b: 3.13us
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250, // 100b: 2.50us
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167, // 101b: 1.67us
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125, // 110b: 1.25us
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100 // 111b: 1.00us
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};
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* P R O T O T Y P E S O F L O C A L F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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VOID
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STATIC
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F14PmVrmLowPowerModeEnable (
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IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
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IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
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IN AMD_CONFIG_PARAMS *StdHeader
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);
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/*----------------------------------------------------------------------------------------
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* E X P O R T E D F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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/*---------------------------------------------------------------------------------------*/
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/**
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* Family 14h core 0 entry point for performing power plane initialization.
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*
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* The steps are as follows:
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* 1. BIOS must initialize D18F3xD8[VSRampSlamTime].
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* 2. BIOS must configure D18F3xA0[PsiVidEn & PsiVid] and
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* D18F3x128[NbPsiVidEn & NbPsiVid].
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* 3. BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1.
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* BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid].
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*
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* @param[in] FamilySpecificServices The current Family Specific Services.
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* @param[in] CpuEarlyParams Service parameters
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* @param[in] StdHeader Config handle for library and services.
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*
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*/
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VOID
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F14PmPwrPlaneInit (
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IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
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IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
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IN AMD_CONFIG_PARAMS *StdHeader
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)
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{
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UINT32 SystemSlewRate;
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UINT32 PciReg;
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UINT32 WaitTime;
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UINT32 VSRampSlamTime;
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PCI_ADDR PciAddress;
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FCRxFE00_6000_STRUCT FCRxFE00_6000;
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// Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements.
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// Voltage Ramp Time = maximum time to change voltage by 12.5mV rounded to the next higher encoding.
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SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <=
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CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ?
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CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate :
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CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate;
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ASSERT (SystemSlewRate != 0);
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// First, calculate the time it takes to change 12.5mV using the VRM slew rate.
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WaitTime = (12500 * 100) / SystemSlewRate;
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if (((12500 * 100) % SystemSlewRate) != 0) {
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WaitTime++;
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}
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// Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds
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// to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable
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// VRM can be.
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for (VSRampSlamTime = (ARRAY_SIZE(F14VSRampSlamWaitTimes)- 1); VSRampSlamTime > 0; VSRampSlamTime--) {
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if (WaitTime <= F14VSRampSlamWaitTimes[VSRampSlamTime]) {
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break;
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}
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}
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if (WaitTime > F14VSRampSlamWaitTimes[0]) {
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// The VRMs on this motherboard are too slow for this CPU.
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IDS_ERROR_TRAP;
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}
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// Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
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PciAddress.AddressValue = CPTC1_PCI_ADDR;
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LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
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((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciReg)->VSRampSlamTime = VSRampSlamTime;
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LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
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// Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid].
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F14PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
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// Step 3 - Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1.
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// Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid].
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FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader);
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F14EarlySampleCoreSupport.F14PowerPlaneInitHook (&FCRxFE00_6000, StdHeader);
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PciAddress.AddressValue = CPTC2_PCI_ADDR;
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LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
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((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
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LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
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((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
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LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
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}
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/*---------------------------------------------------------------------------------------*/
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/**
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* Sets up PSI_L operation.
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*
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* This function implements the AMD_CPU_EARLY_PARAMS.VrmLowPowerThreshold parameter.
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*
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* @param[in] FamilySpecificServices The current Family Specific Services.
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* @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter.
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* @param[in] StdHeader Config handle for library and services.
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*
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*/
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VOID
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STATIC
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F14PmVrmLowPowerModeEnable (
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IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
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IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
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IN AMD_CONFIG_PARAMS *StdHeader
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)
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{
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UINT32 Pstate;
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UINT32 PstateMaxVal;
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UINT32 PstateCurrent;
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UINT32 NextPstateCurrent;
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UINT32 NextPstateCurrentRaw;
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UINT32 PciReg;
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UINT32 PreviousVid;
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UINT32 CurrentVid;
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UINT64 PstateMsr;
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UINT64 PstateLimitMsr;
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BOOLEAN IsPsiEnabled;
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PCI_ADDR PciAddress;
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// Set up PSI_L for VDD
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IsPsiEnabled = FALSE;
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PreviousVid = 0x7F;
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CurrentVid = 0x7F;
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if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) {
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LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &PstateLimitMsr, StdHeader);
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PstateMaxVal = (UINT32) ((PSTATE_CURLIM_MSR *) &PstateLimitMsr)->PstateMaxVal;
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FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) 0, &PstateCurrent, StdHeader);
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for (Pstate = 0; Pstate <= PstateMaxVal; Pstate++) {
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LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader);
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CurrentVid = (UINT32) ((PSTATE_MSR *) &PstateMsr)->CpuVid;
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if (Pstate == PstateMaxVal) {
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NextPstateCurrentRaw = 0;
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NextPstateCurrent = 0;
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} else {
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FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrentRaw, StdHeader);
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NextPstateCurrent = NextPstateCurrentRaw + CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit;
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}
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if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) &&
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(NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) &&
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(CurrentVid != PreviousVid)) {
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IsPsiEnabled = TRUE;
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break;
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} else {
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PstateCurrent = NextPstateCurrentRaw;
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PreviousVid = CurrentVid;
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}
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}
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}
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PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
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LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
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if (IsPsiEnabled) {
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((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVid = CurrentVid;
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((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 1;
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} else {
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((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 0;
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}
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LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
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// Set up NBPSI_L for VDDNB
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PciAddress.AddressValue = CPTC3_PCI_ADDR;
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LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
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if (CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].LowPowerThreshold != 0) {
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((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVid = 0;
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((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 1;
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} else {
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((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 0;
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}
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LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
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}
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