766 lines
18 KiB
C
766 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <delay.h>
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#include <device/mmio.h>
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#include <edid.h>
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#include <lib.h>
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#include <soc/clock.h>
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#include <soc/display/dsi_phy.h>
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#include <soc/display/mdssreg.h>
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#include <soc/display/display_resources.h>
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#include <string.h>
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#include <timer.h>
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#define HAL_DSI_PHY_PLL_READY_TIMEOUT_MS 150 /* ~15 ms */
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#define HAL_DSI_PHY_REFGEN_TIMEOUT_MS 150 /* ~15 ms */
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#define DSI_MAX_REFRESH_RATE 95
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#define DSI_MIN_REFRESH_RATE 15
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#define HAL_DSI_PLL_VCO_MIN_MHZ_2_2_0 1000
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#define S_DIV_ROUND_UP(n, d) \
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(((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
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#define mult_frac(x, numer, denom)( \
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{ \
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typeof(x) quot = (x) / (denom); \
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typeof(x) rem = (x) % (denom); \
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(quot * (numer)) + ((rem * (numer)) / (denom)); \
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} \
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)
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struct dsi_phy_divider_lut_entry_type {
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uint16_t pll_post_div;
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uint16_t phy_post_div;
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};
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/* PLL divider LUTs */
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static struct dsi_phy_divider_lut_entry_type pll_dividerlut_dphy[] = {
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/* pll post div will always be power of 2 */
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{ 2, 11 },
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{ 4, 5 },
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{ 2, 9 },
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{ 8, 2 },
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{ 1, 15 },
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{ 2, 7 },
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{ 1, 13 },
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{ 4, 3 },
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{ 1, 11 },
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{ 2, 5 },
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{ 1, 9 },
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{ 8, 1 },
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{ 1, 7 },
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{ 2, 3 },
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{ 1, 5 },
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{ 4, 1 },
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{ 1, 3 },
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{ 2, 1 },
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{ 1, 1 }
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};
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enum dsi_laneid_type {
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DSI_LANEID_0 = 0,
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DSI_LANEID_1,
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DSI_LANEID_2,
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DSI_LANEID_3,
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DSI_LANEID_CLK,
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DSI_LANEID_MAX,
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DSI_LANEID_FORCE_32BIT = 0x7FFFFFFF
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};
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struct dsi_phy_configtype {
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uint32_t desired_bitclk_freq;
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uint32_t bits_per_pixel;
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uint32_t num_data_lanes;
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uint32_t pclk_divnumerator;
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uint32_t pclk_divdenominator;
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/* pixel clk source select */
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uint32_t phy_post_div;
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uint32_t pll_post_div;
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};
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static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent,
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s32 min_result, bool even)
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{
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s32 v;
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v = (tmax - tmin) * percent;
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v = S_DIV_ROUND_UP(v, 100) + tmin;
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if (even && (v & 0x1))
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return MAX(min_result, v - 1);
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return MAX(min_result, v);
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}
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static void mdss_dsi_phy_reset(void)
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{
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write32(&dsi0_phy->phy_cmn_ctrl1, 0x40);
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udelay(100);
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write32(&dsi0_phy->phy_cmn_ctrl1, 0x0);
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}
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static void mdss_dsi_power_down(void)
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{
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/* power up DIGTOP & PLL */
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write32(&dsi0_phy->phy_cmn_ctrl0, 0x60);
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/* Disable PLL */
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write32(&dsi0_phy->phy_cmn_pll_ctrl, 0x0);
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/* Resync re-time FIFO OFF*/
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write32(&dsi0_phy->phy_cmn_rbuf_ctrl, 0x0);
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}
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static void mdss_dsi_phy_setup_lanephy(enum dsi_laneid_type lane)
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{
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uint32_t reg_val = 0;
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uint32_t lprx_ctrl = 0;
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uint32_t hstx_strength = 0x88;
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uint32_t data_strength_lp_n = 0x5;
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uint32_t data_strength_lp_p = 0x5;
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uint32_t pemph_bottom = 0;
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uint32_t pemph_top = 0;
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uint32_t strength_override = 0;
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uint32_t clk_lane = 0;
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if (lane == DSI_LANEID_CLK)
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clk_lane = 1;
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else
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clk_lane = 0;
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if (lane == DSI_LANEID_0)
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lprx_ctrl = 3;
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/*
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* DSIPHY_STR_LP_N
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* DSIPHY_STR_LP_P
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*/
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reg_val = ((data_strength_lp_n << 0x4) & 0xf0) |
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(data_strength_lp_p & 0x0f);
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_lptx_str_ctrl, reg_val);
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/*
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* DSIPHY_LPRX_EN
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* DSIPHY_CDRX_EN
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* Transition from 0 to 1 for DLN0-3 CLKLN stays 0
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*/
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_lprx_ctrl, 0x0);
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_lprx_ctrl, lprx_ctrl);
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/* Pin Swap */
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_pin_swap, 0x0);
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/*
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* DSIPHY_HSTX_STR_HSTOP
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* DSIPHY_HSTX_STR_HSBOT
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*/
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_hstx_str_ctrl, hstx_strength);
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/* PGM Delay */
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[0], 0x0);
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/* DLN0_CFG1 */
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reg_val = (strength_override << 0x5) & 0x20;
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[1], reg_val);
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/* DLN0_CFG2 */
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reg_val = ((pemph_bottom << 0x04) & 0xf0) |
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(pemph_top & 0x0f);
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[2], reg_val);
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_offset_top_ctrl, 0x0);
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_offset_bot_ctrl, 0x0);
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/*
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* DSIPHY_LPRX_DLY
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* IS_CKLANE
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*/
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reg_val = (clk_lane << 0x07) & 0x80;
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[3], reg_val);
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reg_val = 0;
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if (lane == DSI_LANEID_CLK)
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reg_val = 1;
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write32(&dsi0_phy->phy_ln_regs[lane].dln0_tx_dctrl, reg_val);
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}
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static void mdss_dsi_calculate_phy_timings(struct msm_dsi_phy_ctrl *timing,
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struct dsi_phy_configtype *phy_cfg)
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{
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const unsigned long bit_rate = phy_cfg->desired_bitclk_freq;
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s32 ui, ui_x8;
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s32 tmax, tmin;
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s32 pcnt0 = 50;
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s32 pcnt1 = 50;
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s32 pcnt2 = 10;
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s32 pcnt3 = 30;
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s32 pcnt4 = 10;
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s32 pcnt5 = 2;
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s32 coeff = 1000; /* Precision, should avoid overflow */
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s32 hb_en, hb_en_ckln;
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s32 temp;
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if (!bit_rate)
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return;
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hb_en = 0;
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timing->half_byte_clk_en = 0;
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hb_en_ckln = 0;
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ui = mult_frac(1000000, coeff, bit_rate / 1000);
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ui_x8 = ui << 3;
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temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
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tmin = MAX(temp, 0);
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temp = (95 * coeff) / ui_x8;
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tmax = MAX(temp, 0);
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timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
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temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
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tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
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tmax = (tmin > 255) ? 511 : 255;
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timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
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tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
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temp = 105 * coeff + 12 * ui - 20 * coeff;
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tmax = (temp + 3 * ui) / ui_x8;
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timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
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temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
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tmin = MAX(temp, 0);
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temp = (85 * coeff + 6 * ui) / ui_x8;
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tmax = MAX(temp, 0);
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timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
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temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
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tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
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tmax = 255;
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timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
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tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
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temp = 105 * coeff + 12 * ui - 20 * coeff;
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tmax = (temp / ui_x8) - 1;
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timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
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temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
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timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
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tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
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tmax = 255;
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timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
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temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
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timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
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temp = 60 * coeff + 52 * ui - 43 * ui;
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tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
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tmax = 63;
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timing->clk_post = linear_inter(tmax, tmin, pcnt2, 0, false);
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temp = 8 * ui + (timing->clk_prepare << 3) * ui;
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temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
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temp += hb_en_ckln ? (((timing->hs_rqst << 3) + 4) * ui) :
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(((timing->hs_rqst << 3) + 8) * ui);
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tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
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tmax = 63;
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if (tmin > tmax) {
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temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
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timing->clk_pre = temp >> 1;
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timing->clk_pre_inc_by_2 = 1;
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} else {
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timing->clk_pre = linear_inter(tmax, tmin, pcnt2, 0, false);
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timing->clk_pre_inc_by_2 = 0;
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}
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timing->ta_go = 3;
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timing->ta_sure = 0;
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timing->ta_get = 4;
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printk(BIOS_INFO, "PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n",
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timing->clk_pre, timing->clk_post,
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timing->clk_pre_inc_by_2, timing->clk_zero,
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timing->clk_trail, timing->clk_prepare, timing->hs_exit,
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timing->hs_zero, timing->hs_prepare, timing->hs_trail,
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timing->hs_rqst);
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}
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static enum cb_err mdss_dsi_phy_timings(struct msm_dsi_phy_ctrl *phy_timings)
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{
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uint32_t reg_val = 0;
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/*
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* Step 4 Common block including GlobalTiming Parameters
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* BYTECLK_SEL
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*/
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reg_val = (0x02 << 3) & 0x18;
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write32(&dsi0_phy->phy_cmn_glbl_ctrl, reg_val);
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/* VREG_CTRL */
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write32(&dsi0_phy->phy_cmn_vreg_ctrl, 0x59);
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/*HALFBYTECLK_EN*/
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write32(&dsi0_phy->phy_cmn_timing_ctrl[0], phy_timings->half_byte_clk_en);
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/* T_CLK_ZERO */
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write32(&dsi0_phy->phy_cmn_timing_ctrl[1], phy_timings->clk_zero);
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/* T_CLK_PREPARE */
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write32(&dsi0_phy->phy_cmn_timing_ctrl[2], phy_timings->clk_prepare);
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/* T_CLK_TRAIL */
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write32(&dsi0_phy->phy_cmn_timing_ctrl[3], phy_timings->clk_trail);
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/* T_HS_EXIT */
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write32(&dsi0_phy->phy_cmn_timing_ctrl[4], phy_timings->hs_exit);
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/* T_HS_ZERO */
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write32(&dsi0_phy->phy_cmn_timing_ctrl[5], phy_timings->hs_zero);
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/* T_HS_PREPARE */
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write32(&dsi0_phy->phy_cmn_timing_ctrl[6], phy_timings->hs_prepare);
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/* T_HS_TRAIL */
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write32(&dsi0_phy->phy_cmn_timing_ctrl[7], phy_timings->hs_trail);
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/* T_HS_RQST */
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write32(&dsi0_phy->phy_cmn_timing_ctrl[8], phy_timings->hs_rqst);
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/* T_TA_GO & T_TA_SURE */
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write32(&dsi0_phy->phy_cmn_timing_ctrl[9],
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phy_timings->ta_sure << 3 | phy_timings->ta_go);
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/* T_TA_GET */
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write32(&dsi0_phy->phy_cmn_timing_ctrl[10], phy_timings->ta_get);
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/*DSIPHY_TRIG3_CMD*/
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write32(&dsi0_phy->phy_cmn_timing_ctrl[11], 0x0);
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/* DSI clock out timing ctrl T_CLK_PRE & T_CLK_POST*/
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reg_val = ((phy_timings->clk_post << 8) | phy_timings->clk_pre);
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write32(&dsi0->clkout_timing_ctrl, reg_val);
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/* DCTRL */
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write32(&dsi0_phy->phy_cmn_ctrl2, 0x40);
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return CB_SUCCESS;
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}
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static enum cb_err dsi_phy_waitforrefgen(void)
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{
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uint32_t timeout = HAL_DSI_PHY_REFGEN_TIMEOUT_MS;
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uint32_t refgen = 0;
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enum cb_err ret = CB_SUCCESS;
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while (!refgen) {
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refgen = (read32(&dsi0_phy->phy_cmn_phy_status) & 0x1);
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if (!refgen) {
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udelay(100);
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timeout--;
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if (!timeout) {
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/* timeout while polling the lock status */
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ret = CB_ERR;
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break;
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}
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}
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}
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return ret;
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}
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static enum cb_err mdss_dsi_phy_commit(void)
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{
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enum cb_err ret = CB_SUCCESS;
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ret = dsi_phy_waitforrefgen();
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if (ret) {
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printk(BIOS_ERR, "%s: waitforrefgen error\n", __func__);
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return ret;
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}
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mdss_dsi_power_down();
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/* Remove PLL, DIG and all lanes from pwrdn */
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write32(&dsi0_phy->phy_cmn_ctrl0, 0x7F);
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/* Lane enable */
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write32(&dsi0_phy->phy_cmn_dsi_lane_ctrl0, 0x1F);
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mdss_dsi_phy_setup_lanephy(DSI_LANEID_0);
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mdss_dsi_phy_setup_lanephy(DSI_LANEID_1);
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mdss_dsi_phy_setup_lanephy(DSI_LANEID_2);
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mdss_dsi_phy_setup_lanephy(DSI_LANEID_3);
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mdss_dsi_phy_setup_lanephy(DSI_LANEID_CLK);
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return ret;
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}
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static void mdss_dsi_phy_setup(void)
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{
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/* First reset phy */
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mdss_dsi_phy_reset();
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/* commit phy settings */
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mdss_dsi_phy_commit();
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}
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static void dsi_phy_resync_fifo(void)
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{
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/* Resync FIFO*/
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write32(&dsi0_phy->phy_cmn_rbuf_ctrl, 0x1);
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}
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static void dsi_phy_pll_global_clk_enable(bool enable)
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{
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uint32_t clk_cfg = read32(&dsi0_phy->phy_cmn_clk_cfg1);
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uint32_t clk_enable = 0;
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/* Set CLK_EN */
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if (enable)
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clk_enable = 1;
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clk_cfg &= ~0x20;
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clk_cfg |= ((clk_enable << 0x5) & 0x20);
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/* clk cfg1 */
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write32(&dsi0_phy->phy_cmn_clk_cfg1, clk_cfg);
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}
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static enum cb_err dsi_phy_pll_lock_detect(void)
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{
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enum cb_err ret = CB_SUCCESS;
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/* Enable PLL */
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write32(&dsi0_phy->phy_cmn_pll_ctrl, 0x1);
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/* Wait for Lock */
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if (!wait_us(15000, read32(&phy_pll_qlink->pll_common_status_one) & 0x1)) {
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/* timeout while polling the lock status */
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ret = CB_ERR;
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printk(BIOS_ERR, "dsi pll lock detect timedout, error.\n");
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}
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return ret;
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}
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static void dsi_phy_toggle_dln3_tx_dctrl(void)
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{
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uint32_t reg_val = 0;
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reg_val = read32(&dsi0_phy->phy_ln_regs[DSI_LANEID_3].dln0_tx_dctrl);
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/* clear bit 0 and keep all other bits including bit 2 */
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reg_val &= ~0x01;
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/* toggle bit 0 */
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write32(&dsi0_phy->phy_ln_regs[DSI_LANEID_3].dln0_tx_dctrl, (0x01 | reg_val));
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write32(&dsi0_phy->phy_ln_regs[DSI_LANEID_3].dln0_tx_dctrl, 0x4);
|
|
}
|
|
|
|
static void dsi_phy_pll_set_source(void)
|
|
{
|
|
uint32_t clk_cfg = read32(&dsi0_phy->phy_cmn_clk_cfg1);
|
|
uint32_t dsi_clksel = 1;
|
|
|
|
clk_cfg &= ~0x03;
|
|
clk_cfg |= ((dsi_clksel) & 0x3);
|
|
|
|
/* clk cfg1 */
|
|
write32(&dsi0_phy->phy_cmn_clk_cfg1, clk_cfg);
|
|
}
|
|
|
|
static void dsi_phy_pll_bias_enable(bool enable)
|
|
{
|
|
uint32_t reg_val = 0;
|
|
|
|
/* Set BIAS_EN_MUX, BIAS_EN */
|
|
if (enable)
|
|
reg_val = (0x01 << 6) | (0x01 << 7);
|
|
|
|
/* pll system muxes */
|
|
write32(&phy_pll_qlink->pll_system_muxes, reg_val);
|
|
|
|
}
|
|
|
|
static void dsi_phy_mnd_divider(struct dsi_phy_configtype *phy_cfg)
|
|
{
|
|
uint32_t m_val = 1;
|
|
uint32_t n_val = 1;
|
|
|
|
if (phy_cfg->bits_per_pixel == 18) {
|
|
switch (phy_cfg->num_data_lanes) {
|
|
case 1:
|
|
case 2:
|
|
m_val = 2;
|
|
n_val = 3;
|
|
break;
|
|
case 4:
|
|
m_val = 4;
|
|
n_val = 9;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
} else if ((phy_cfg->bits_per_pixel == 16) &&
|
|
(phy_cfg->num_data_lanes == 3)) {
|
|
m_val = 3;
|
|
n_val = 8;
|
|
} else if ((phy_cfg->bits_per_pixel == 30) &&
|
|
(phy_cfg->num_data_lanes == 4)) {
|
|
m_val = 2;
|
|
n_val = 3;
|
|
}
|
|
|
|
/*Save M/N info */
|
|
phy_cfg->pclk_divnumerator = m_val;
|
|
phy_cfg->pclk_divdenominator = n_val;
|
|
}
|
|
|
|
static uint32_t dsi_phy_dsiclk_divider(struct dsi_phy_configtype *phy_cfg)
|
|
{
|
|
uint32_t m_val = phy_cfg->pclk_divnumerator;
|
|
uint32_t n_val = phy_cfg->pclk_divdenominator;
|
|
uint32_t div_ctrl = 0;
|
|
|
|
div_ctrl = (m_val * phy_cfg->bits_per_pixel) /
|
|
(n_val * phy_cfg->num_data_lanes * 2);
|
|
|
|
return div_ctrl;
|
|
}
|
|
|
|
|
|
static unsigned long dsi_phy_calc_clk_divider(struct dsi_phy_configtype *phy_cfg)
|
|
{
|
|
bool div_found = false;
|
|
uint32_t m_val = 1;
|
|
uint32_t n_val = 1;
|
|
uint32_t div_ctrl = 0;
|
|
uint32_t reg_val = 0;
|
|
uint32_t pll_post_div = 0;
|
|
uint32_t phy_post_div = 0;
|
|
uint64_t vco_freq_hz = 0;
|
|
uint64_t fval = 0;
|
|
uint64_t pll_output_freq_hz;
|
|
uint64_t desired_bitclk_hz;
|
|
uint64_t min_vco_freq_hz = 0;
|
|
uint32_t lut_max;
|
|
int i;
|
|
struct dsi_phy_divider_lut_entry_type *lut;
|
|
|
|
/* use 1000Mhz */
|
|
min_vco_freq_hz = (HAL_DSI_PLL_VCO_MIN_MHZ_2_2_0 * 1000000);
|
|
|
|
dsi_phy_mnd_divider(phy_cfg);
|
|
|
|
m_val = phy_cfg->pclk_divnumerator;
|
|
n_val = phy_cfg->pclk_divdenominator;
|
|
|
|
/* Desired clock in MHz */
|
|
desired_bitclk_hz = (uint64_t)phy_cfg->desired_bitclk_freq;
|
|
|
|
/* D Phy */
|
|
lut = pll_dividerlut_dphy;
|
|
lut_max = ARRAY_SIZE(pll_dividerlut_dphy);
|
|
lut += (lut_max - 1);
|
|
|
|
/* PLL Post Div - from LUT
|
|
* Check the LUT in reverse order
|
|
*/
|
|
for (i = lut_max - 1; i >= 0; i--, lut--) {
|
|
fval = (uint64_t)lut->phy_post_div *
|
|
(uint64_t)lut->pll_post_div;
|
|
if (fval) {
|
|
if ((desired_bitclk_hz * fval) > min_vco_freq_hz) {
|
|
/* Range found */
|
|
pll_post_div = lut->pll_post_div;
|
|
phy_post_div = lut->phy_post_div;
|
|
div_found = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (div_found) {
|
|
phy_cfg->pll_post_div = pll_post_div;
|
|
phy_cfg->phy_post_div = phy_post_div;
|
|
|
|
/*div_ctrl_7_4 */
|
|
div_ctrl = dsi_phy_dsiclk_divider(phy_cfg);
|
|
|
|
/* DIV_CTRL_7_4 DIV_CTRL_3_0
|
|
* (DIV_CTRL_3_0 = PHY post divider ratio)
|
|
*/
|
|
reg_val = (div_ctrl << 0x04) & 0xf0;
|
|
reg_val |= (phy_post_div & 0x0f);
|
|
write32(&dsi0_phy->phy_cmn_clk_cfg0, reg_val);
|
|
|
|
/* PLL output frequency = desired_bitclk_hz * phy_post_div */
|
|
pll_output_freq_hz = desired_bitclk_hz * phy_post_div;
|
|
|
|
/* VCO output freq*/
|
|
vco_freq_hz = pll_output_freq_hz * pll_post_div;
|
|
|
|
}
|
|
|
|
return (unsigned long)vco_freq_hz;
|
|
}
|
|
|
|
static void dsi_phy_pll_outputdiv_rate(struct dsi_phy_configtype *pll_cfg)
|
|
{
|
|
/* Output divider */
|
|
uint32_t pll_post_div = 0;
|
|
uint32_t reg_val = 0;
|
|
|
|
pll_post_div = log2(pll_cfg->pll_post_div);
|
|
reg_val = pll_post_div & 0x3;
|
|
write32(&phy_pll_qlink->pll_outdiv_rate, reg_val);
|
|
}
|
|
|
|
static enum cb_err dsi_phy_pll_calcandcommit(struct dsi_phy_configtype *phy_cfg)
|
|
{
|
|
unsigned long vco_freq_hz;
|
|
enum cb_err ret = CB_SUCCESS;
|
|
|
|
/* validate input parameters */
|
|
if (!phy_cfg) {
|
|
return CB_ERR;
|
|
} else if ((phy_cfg->bits_per_pixel != 16) &&
|
|
(phy_cfg->bits_per_pixel != 18) &&
|
|
(phy_cfg->bits_per_pixel != 24)) {
|
|
/* Unsupported pixel bit depth */
|
|
return CB_ERR;
|
|
} else if ((phy_cfg->num_data_lanes == 0) ||
|
|
(phy_cfg->num_data_lanes > 4)) {
|
|
/* Illegal number of DSI data lanes */
|
|
return CB_ERR;
|
|
}
|
|
|
|
vco_freq_hz = dsi_phy_calc_clk_divider(phy_cfg);
|
|
if (!vco_freq_hz) {
|
|
/* bitclock too low - unsupported */
|
|
printk(BIOS_ERR, "vco_freq_hz is 0, unsupported\n");
|
|
return CB_ERR;
|
|
}
|
|
|
|
/* Enable PLL bias */
|
|
dsi_phy_pll_bias_enable(true);
|
|
|
|
/* Set byte clk source */
|
|
dsi_phy_pll_set_source();
|
|
|
|
dsi_phy_pll_outputdiv_rate(phy_cfg);
|
|
dsi_phy_pll_vco_10nm_set_rate(vco_freq_hz);
|
|
dsi_phy_toggle_dln3_tx_dctrl();
|
|
|
|
/* Steps 6,7 Start PLL & Lock */
|
|
if (ret == CB_SUCCESS)
|
|
ret = dsi_phy_pll_lock_detect();
|
|
|
|
/* Step 8 - Resync Data Paths */
|
|
if (ret == CB_SUCCESS) {
|
|
/* Global clock enable */
|
|
dsi_phy_pll_global_clk_enable(true);
|
|
|
|
/* Resync FIFOs */
|
|
dsi_phy_resync_fifo();
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint32_t dsi_calc_desired_bitclk(struct edid *edid, uint32_t num_lines, uint32_t bpp)
|
|
{
|
|
uint64_t desired_bclk = 0;
|
|
uint32_t pixel_clock_in_hz;
|
|
|
|
pixel_clock_in_hz = edid->mode.pixel_clock * KHz;
|
|
if (num_lines) {
|
|
desired_bclk = pixel_clock_in_hz * (uint64_t)bpp;
|
|
desired_bclk = desired_bclk/(uint64_t)(num_lines);
|
|
}
|
|
|
|
printk(BIOS_INFO, "Desired bitclock: %uHz\n", (uint32_t)desired_bclk);
|
|
return (uint32_t)desired_bclk;
|
|
}
|
|
|
|
static enum cb_err mdss_dsi_phy_pll_setup(struct edid *edid,
|
|
uint32_t num_of_lanes, uint32_t bpp)
|
|
{
|
|
struct dsi_phy_configtype phy_cfg;
|
|
struct msm_dsi_phy_ctrl phy_timings;
|
|
enum cb_err ret;
|
|
|
|
/* Setup the PhyStructure */
|
|
memset(&phy_cfg, 0, sizeof(struct dsi_phy_configtype));
|
|
memset(&phy_timings, 0, sizeof(struct msm_dsi_phy_ctrl));
|
|
|
|
phy_cfg.bits_per_pixel = bpp;
|
|
phy_cfg.num_data_lanes = num_of_lanes;
|
|
|
|
/* desired DSI PLL bit clk freq in Hz */
|
|
phy_cfg.desired_bitclk_freq = dsi_calc_desired_bitclk(edid, num_of_lanes, bpp);
|
|
|
|
ret = dsi_phy_pll_calcandcommit(&phy_cfg);
|
|
if (ret)
|
|
return ret;
|
|
mdss_dsi_calculate_phy_timings(&phy_timings, &phy_cfg);
|
|
ret = mdss_dsi_phy_timings(&phy_timings);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static enum cb_err enable_dsi_clk(void)
|
|
{
|
|
enum cb_err ret;
|
|
uint32_t i = 0;
|
|
struct mdp_external_clock_entry clks[] = {
|
|
{.clk_type = MDSS_CLK_ESC0, .clk_secondary_source = 1},
|
|
{.clk_type = MDSS_CLK_PCLK0, .clk_source = 1},
|
|
{.clk_type = MDSS_CLK_BYTE0, .clk_source = 1},
|
|
{.clk_type = MDSS_CLK_BYTE0_INTF, .clk_source = 1,
|
|
.clk_div = 2, .source_div = 2},
|
|
};
|
|
|
|
for (i = 0; i < ARRAY_SIZE(clks); i++) {
|
|
/* Set Ext Source */
|
|
ret = mdss_clock_configure(clks[i].clk_type,
|
|
clks[i].clk_source,
|
|
clks[i].clk_div,
|
|
clks[i].clk_pll_m,
|
|
clks[i].clk_pll_n,
|
|
clks[i].clk_pll_2d);
|
|
if (ret) {
|
|
printk(BIOS_ERR,
|
|
"mdss_clock_configure failed for %u\n",
|
|
clks[i].clk_type);
|
|
return CB_ERR;
|
|
}
|
|
|
|
ret = mdss_clock_enable(clks[i].clk_type);
|
|
if (ret) {
|
|
printk(BIOS_ERR,
|
|
"mdss_clock_enable failed for %u\n",
|
|
clks[i].clk_type);
|
|
return CB_ERR;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
enum cb_err mdss_dsi_phy_10nm_init(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp)
|
|
{
|
|
enum cb_err ret;
|
|
|
|
/* Phy set up */
|
|
mdss_dsi_phy_setup();
|
|
ret = mdss_dsi_phy_pll_setup(edid, num_of_lanes, bpp);
|
|
enable_dsi_clk();
|
|
|
|
return ret;
|
|
}
|