495 lines
15 KiB
C
495 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <string.h>
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#include <device/mmio.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/iomap.h>
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#include <soc/pcr.h>
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#include <soc/soc_util.h>
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#include <soc/gpio_dnv.h>
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// Community PadOwnOffset HostOwnOffset
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// GpiIsOffset
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// GpiIeOffset GpiGpeStsOffset GpiGpeEnOffset
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// SmiStsOffset
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// SmiEnOffset NmiStsOffset NmiEnOffset
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// PadCfgLockOffset
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// PadCfgLockTxOffset PadCfgOffset PadPerGroup
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static const struct GPIO_GROUP_INFO mGpioGroupInfo[] = {
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{PID_GPIOCOM0, R_PCH_PCR_GPIO_NC_PAD_OWN, R_PCH_PCR_GPIO_NC_HOSTSW_OWN,
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R_PCH_PCR_GPIO_NC_GPI_IS, R_PCH_PCR_GPIO_NC_GPI_IE,
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R_PCH_PCR_GPIO_NC_GPI_GPE_STS, R_PCH_PCR_GPIO_NC_GPI_GPE_EN,
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R_PCH_PCR_GPIO_NC_SMI_STS, R_PCH_PCR_GPIO_NC_SMI_EN,
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R_PCH_PCR_GPIO_NC_NMI_STS, R_PCH_PCR_GPIO_NC_NMI_EN,
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R_PCH_PCR_GPIO_NC_PADCFGLOCK, R_PCH_PCR_GPIO_NC_PADCFGLOCKTX,
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R_PCH_PCR_GPIO_NC_PADCFG_OFFSET,
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V_PCH_GPIO_NC_PAD_MAX}, // DNV NORTH_ALL
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{PID_GPIOCOM1, R_PCH_PCR_GPIO_SC_DFX_PAD_OWN,
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R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN, R_PCH_PCR_GPIO_SC_DFX_GPI_IS,
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R_PCH_PCR_GPIO_SC_DFX_GPI_IE, R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS,
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R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY,
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NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY,
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NO_REGISTER_FOR_PROPERTY, R_PCH_PCR_GPIO_SC_DFX_PADCFGLOCK,
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R_PCH_PCR_GPIO_SC_DFX_PADCFGLOCKTX,
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R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET,
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V_PCH_GPIO_SC_DFX_PAD_MAX}, // DNV SOUTH_DFX
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{PID_GPIOCOM1, R_PCH_PCR_GPIO_SC0_PAD_OWN,
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R_PCH_PCR_GPIO_SC0_HOSTSW_OWN, R_PCH_PCR_GPIO_SC0_GPI_IS,
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R_PCH_PCR_GPIO_SC0_GPI_IE, R_PCH_PCR_GPIO_SC0_GPI_GPE_STS,
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R_PCH_PCR_GPIO_SC0_GPI_GPE_EN, R_PCH_PCR_GPIO_SC0_SMI_STS,
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R_PCH_PCR_GPIO_SC0_SMI_EN, R_PCH_PCR_GPIO_SC0_NMI_STS,
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R_PCH_PCR_GPIO_SC0_NMI_EN, R_PCH_PCR_GPIO_SC0_PADCFGLOCK,
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R_PCH_PCR_GPIO_SC0_PADCFGLOCKTX, R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET,
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V_PCH_GPIO_SC0_PAD_MAX}, // DNV South Community 0
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{PID_GPIOCOM1, R_PCH_PCR_GPIO_SC1_PAD_OWN,
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R_PCH_PCR_GPIO_SC1_HOSTSW_OWN, R_PCH_PCR_GPIO_SC1_GPI_IS,
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R_PCH_PCR_GPIO_SC1_GPI_IE, R_PCH_PCR_GPIO_SC1_GPI_GPE_STS,
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R_PCH_PCR_GPIO_SC1_GPI_GPE_EN, R_PCH_PCR_GPIO_SC1_SMI_STS,
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R_PCH_PCR_GPIO_SC1_SMI_EN, R_PCH_PCR_GPIO_SC1_NMI_STS,
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R_PCH_PCR_GPIO_SC1_NMI_EN, R_PCH_PCR_GPIO_SC1_PADCFGLOCK,
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R_PCH_PCR_GPIO_SC1_PADCFGLOCKTX, R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET,
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V_PCH_GPIO_SC1_PAD_MAX}, // DNV South Community 1
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};
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/* Retrieve address and length of GPIO info table */
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static struct GPIO_GROUP_INFO *
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GpioGetGroupInfoTable(uint32_t *GpioGroupInfoTableLength)
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{
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*GpioGroupInfoTableLength = ARRAY_SIZE(mGpioGroupInfo);
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return (struct GPIO_GROUP_INFO *)mGpioGroupInfo;
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}
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/* Get Gpio Pad Ownership */
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static void GpioGetPadOwnership(GPIO_PAD GpioPad, GPIO_PAD_OWN *PadOwnVal)
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{
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uint32_t Mask;
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uint32_t RegOffset;
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uint32_t GroupIndex;
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uint32_t PadNumber;
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struct GPIO_GROUP_INFO *GpioGroupInfo;
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uint32_t GpioGroupInfoLength;
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uint32_t PadOwnRegValue;
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GroupIndex = GPIO_GET_GROUP_INDEX_FROM_PAD(GpioPad);
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PadNumber = GPIO_GET_PAD_NUMBER(GpioPad);
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GpioGroupInfo = GpioGetGroupInfoTable(&GpioGroupInfoLength);
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//
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// Check if group argument exceeds GPIO GROUP INFO array
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//
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if ((uint32_t)GroupIndex >= GpioGroupInfoLength) {
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printk(BIOS_ERR, "GPIO ERROR: Group argument (%d) exceeds GPIO "
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"group range\n",
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GroupIndex);
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return;
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}
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//
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// Check if legal pin number
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//
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if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
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printk(BIOS_ERR, "GPIO ERROR: Pin number (%d) exceeds possible "
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"range for this group\n",
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PadNumber);
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return;
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}
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//
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// Calculate RegOffset using Pad Ownership offset and GPIO Pad number.
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// One DWord register contains information for 8 pads.
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//
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RegOffset =
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GpioGroupInfo[GroupIndex].PadOwnOffset + (PadNumber >> 3) * 0x4;
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//
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// Calculate pad bit position within DWord register
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//
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PadNumber %= 8;
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Mask = ((1 << 1) | (1 << 0)) << (PadNumber * 4);
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PadOwnRegValue = read32((void *)PCH_PCR_ADDRESS(
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GpioGroupInfo[GroupIndex].Community, RegOffset));
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*PadOwnVal = (GPIO_PAD_OWN)((PadOwnRegValue & Mask) >> (PadNumber * 4));
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}
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void gpio_configure_dnv_pads(const struct dnv_pad_config *gpio, size_t num)
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{
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/* Return if gpio not valid */
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if ((gpio == NULL) || (num == 0))
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return;
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uint32_t Index;
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uint32_t Dw0Reg;
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uint32_t Dw0RegMask;
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uint32_t Dw1Reg;
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uint32_t Dw1RegMask;
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uint32_t PadCfgReg;
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uint64_t HostSoftOwnReg[V_PCH_GPIO_GROUP_MAX];
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uint64_t HostSoftOwnRegMask[V_PCH_GPIO_GROUP_MAX];
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uint64_t GpiGpeEnReg[V_PCH_GPIO_GROUP_MAX];
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uint64_t GpiGpeEnRegMask[V_PCH_GPIO_GROUP_MAX];
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struct GPIO_GROUP_INFO *GpioGroupInfo;
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uint32_t GpioGroupInfoLength;
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GPIO_PAD GpioGroupOffset;
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uint32_t NumberOfGroups;
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GPIO_PAD_OWN PadOwnVal;
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struct dnv_pad_config *GpioData;
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GPIO_PAD Group;
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uint32_t GroupIndex;
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uint32_t PadNumber;
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uint32_t FinalValue;
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uint32_t Data32;
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uint32_t PadMode1, PadMode2;
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PadOwnVal = GpioPadOwnHost;
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memset(HostSoftOwnReg, 0, sizeof(HostSoftOwnReg));
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memset(HostSoftOwnRegMask, 0, sizeof(HostSoftOwnRegMask));
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memset(GpiGpeEnReg, 0, sizeof(GpiGpeEnReg));
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memset(GpiGpeEnRegMask, 0, sizeof(GpiGpeEnRegMask));
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GpioGroupInfo = GpioGetGroupInfoTable(&GpioGroupInfoLength);
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GpioGroupOffset = GPIO_DNV_GROUP_MIN;
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NumberOfGroups = V_PCH_GPIO_GROUP_MAX;
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for (Index = 0; Index < (uint32_t)num; Index++) {
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Dw0RegMask = 0;
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Dw0Reg = 0;
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Dw1RegMask = 0;
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Dw1Reg = 0;
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GpioData = (struct dnv_pad_config *)&(gpio[Index]);
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Group = GPIO_GET_GROUP_FROM_PAD(GpioData->GpioPad);
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GroupIndex = GPIO_GET_GROUP_INDEX_FROM_PAD(GpioData->GpioPad);
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PadNumber = GPIO_GET_PAD_NUMBER(GpioData->GpioPad);
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//
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// Check if group index argument exceeds GPIO group index range
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//
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if (GroupIndex >= V_PCH_GPIO_GROUP_MAX) {
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printk(BIOS_ERR, "GPIO ERROR: Invalid Group Index "
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"(GroupIndex=%d, Pad=%d)!\n",
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GroupIndex, PadNumber);
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continue;
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}
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//
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// Check if group argument exceeds GPIO group range
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//
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if ((Group < GpioGroupOffset) ||
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(Group >= NumberOfGroups + GpioGroupOffset)) {
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printk(BIOS_ERR,
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"GPIO ERROR: Invalid Group (Group=%d)!\n",
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Group);
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return;
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}
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//
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// Check if legal pin number
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//
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if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
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printk(BIOS_ERR, "GPIO ERROR: Invalid PadNumber "
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"(PadNumber=%d)!\n",
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PadNumber);
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return;
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}
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//
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// Check if selected GPIO Pad is not owned by CSME/ISH
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//
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GpioGetPadOwnership(GpioData->GpioPad, &PadOwnVal);
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if (PadOwnVal != GpioPadOwnHost) {
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printk(BIOS_ERR, "GPIO WARNING: Accessing pad not "
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"owned by host (Group=%d, Pad=%d)!",
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GroupIndex, PadNumber);
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if (PadOwnVal == GpioPadOwnCsme)
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printk(BIOS_ERR, "The owner is CSME\n");
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else if (PadOwnVal == GpioPadOwnIsh)
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printk(BIOS_ERR, "The owner is ISH\n");
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printk(BIOS_ERR, "** Please make sure the GPIO usage "
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"in sync between CSME/ISH and Host IA "
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"FW configuration.\n");
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printk(BIOS_ERR, "** All the GPIO occupied by CSME/ISH "
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"should not do any configuration by "
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"Host IA FW.\n");
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continue;
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}
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//
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// Configure Reset Type (PadRstCfg)
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//
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Dw0RegMask |=
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((((GpioData->GpioConfig.PowerConfig &
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GPIO_CONF_RESET_MASK) >>
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GPIO_CONF_RESET_BIT_POS) == GpioHardwareDefault)
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? 0x0
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: B_PCH_GPIO_RST_CONF);
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Dw0Reg |= (((GpioData->GpioConfig.PowerConfig &
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GPIO_CONF_RESET_MASK) >>
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(GPIO_CONF_RESET_BIT_POS + 1))
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<< N_PCH_GPIO_RST_CONF);
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//
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// Configure how interrupt is triggered (RxEvCfg)
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//
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Dw0RegMask |=
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((((GpioData->GpioConfig.InterruptConfig &
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GPIO_CONF_INT_TRIG_MASK) >>
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GPIO_CONF_INT_TRIG_BIT_POS) == GpioHardwareDefault)
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? 0x0
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: B_PCH_GPIO_RX_LVL_EDG);
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Dw0Reg |= (((GpioData->GpioConfig.InterruptConfig &
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GPIO_CONF_INT_TRIG_MASK) >>
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(GPIO_CONF_INT_TRIG_BIT_POS + 1))
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<< N_PCH_GPIO_RX_LVL_EDG);
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//
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// Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI)
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//
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Dw0RegMask |=
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((((GpioData->GpioConfig.InterruptConfig &
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GPIO_CONF_INT_ROUTE_MASK) >>
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GPIO_CONF_INT_ROUTE_BIT_POS) == GpioHardwareDefault)
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? 0x0
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: (B_PCH_GPIO_RX_NMI_ROUTE |
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B_PCH_GPIO_RX_SCI_ROUTE |
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B_PCH_GPIO_RX_SMI_ROUTE |
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B_PCH_GPIO_RX_APIC_ROUTE));
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Dw0Reg |= (((GpioData->GpioConfig.InterruptConfig &
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GPIO_CONF_INT_ROUTE_MASK) >>
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(GPIO_CONF_INT_ROUTE_BIT_POS + 1))
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<< N_PCH_GPIO_RX_NMI_ROUTE);
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// If CFIO is not Working as GPIO mode, Don't move TxDisable and
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// RxDisable
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if (GpioData->GpioConfig.PadMode == GpioPadModeGpio) {
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//
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// Configure GPIO direction (GPIORxDis and GPIOTxDis)
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//
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Dw0RegMask |= ((((GpioData->GpioConfig.Direction &
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GPIO_CONF_DIR_MASK) >>
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GPIO_CONF_DIR_BIT_POS) ==
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GpioHardwareDefault)
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? 0x0
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: (B_PCH_GPIO_RXDIS |
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B_PCH_GPIO_TXDIS));
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Dw0Reg |= (((GpioData->GpioConfig.Direction &
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GPIO_CONF_DIR_MASK) >>
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(GPIO_CONF_DIR_BIT_POS + 1))
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<< N_PCH_GPIO_TXDIS);
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}
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//
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// Configure GPIO input inversion (RXINV)
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//
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Dw0RegMask |= ((((GpioData->GpioConfig.Direction &
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GPIO_CONF_INV_MASK) >>
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GPIO_CONF_INV_BIT_POS) == GpioHardwareDefault)
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? 0x0
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: B_PCH_GPIO_RXINV);
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Dw0Reg |= (((GpioData->GpioConfig.Direction &
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GPIO_CONF_INV_MASK) >>
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(GPIO_CONF_INV_BIT_POS + 1))
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<< N_PCH_GPIO_RXINV);
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//
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// Configure GPIO output state (GPIOTxState)
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//
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Dw0RegMask |=
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((((GpioData->GpioConfig.OutputState &
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GPIO_CONF_OUTPUT_MASK) >>
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GPIO_CONF_OUTPUT_BIT_POS) == GpioHardwareDefault)
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? 0x0
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: B_PCH_GPIO_TX_STATE);
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Dw0Reg |= (((GpioData->GpioConfig.OutputState &
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GPIO_CONF_OUTPUT_MASK) >>
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(GPIO_CONF_OUTPUT_BIT_POS + 1))
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<< N_PCH_GPIO_TX_STATE);
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//
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// Configure GPIO RX raw override to '1' (RXRAW1)
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//
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Dw0RegMask |=
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((((GpioData->GpioConfig.OtherSettings &
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GPIO_CONF_RXRAW_MASK) >>
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GPIO_CONF_RXRAW_BIT_POS) == GpioHardwareDefault)
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? 0x0
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: B_PCH_GPIO_RX_RAW1);
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Dw0Reg |= (((GpioData->GpioConfig.OtherSettings &
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GPIO_CONF_RXRAW_MASK) >>
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(GPIO_CONF_RXRAW_BIT_POS + 1))
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<< N_PCH_GPIO_RX_RAW1);
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//
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// Configure GPIO Pad Mode (PMode)
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//
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Dw0RegMask |=
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((((GpioData->GpioConfig.PadMode &
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GPIO_CONF_PAD_MODE_MASK) >>
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GPIO_CONF_PAD_MODE_BIT_POS) == GpioHardwareDefault)
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? 0x0
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: B_PCH_GPIO_PAD_MODE);
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Dw0Reg |= (((GpioData->GpioConfig.PadMode &
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GPIO_CONF_PAD_MODE_MASK) >>
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(GPIO_CONF_PAD_MODE_BIT_POS + 1))
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<< N_PCH_GPIO_PAD_MODE);
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//
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// Configure GPIO termination (Term)
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//
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Dw1RegMask |= ((((GpioData->GpioConfig.ElectricalConfig &
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GPIO_CONF_TERM_MASK) >>
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GPIO_CONF_TERM_BIT_POS) == GpioHardwareDefault)
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? 0x0
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: B_PCH_GPIO_TERM);
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Dw1Reg |= (((GpioData->GpioConfig.ElectricalConfig &
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GPIO_CONF_TERM_MASK) >>
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(GPIO_CONF_TERM_BIT_POS + 1))
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<< N_PCH_GPIO_TERM);
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//
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// Configure GPIO pad tolerance (padtol)
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//
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Dw1RegMask |=
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((((GpioData->GpioConfig.ElectricalConfig &
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GPIO_CONF_PADTOL_MASK) >>
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GPIO_CONF_PADTOL_BIT_POS) == GpioHardwareDefault)
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? 0x0
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: B_PCH_GPIO_PADTOL);
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Dw1Reg |= (((GpioData->GpioConfig.ElectricalConfig &
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GPIO_CONF_PADTOL_MASK) >>
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(GPIO_CONF_PADTOL_BIT_POS + 1))
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<< N_PCH_GPIO_PADTOL);
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//
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// Check for additional requirements on setting PADCFG register
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//
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//
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// Create PADCFG register offset using group and pad number
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//
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PadCfgReg = 0x8 * PadNumber +
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GpioGroupInfo[GroupIndex].PadCfgOffset;
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Data32 = read32((void *)PCH_PCR_ADDRESS(
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GpioGroupInfo[GroupIndex].Community, PadCfgReg));
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FinalValue = ((Data32 & (~Dw0RegMask)) | Dw0Reg);
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PadMode1 =
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(Data32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE;
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PadMode2 =
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(Dw0Reg & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE;
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if (((Data32 & B_PCH_GPIO_PAD_MODE) !=
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(FinalValue & B_PCH_GPIO_PAD_MODE)) ||
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(PadMode2 == 0)) {
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printk(BIOS_DEBUG, "Changing GpioPad PID: %x Offset: "
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"0x%x PadModeP1: %d P2: %d ",
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GpioGroupInfo[GroupIndex].Community, PadCfgReg,
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PadMode1, PadMode2);
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printk(BIOS_DEBUG, "R: 0x%08x Fx%08x !\n", Data32,
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FinalValue);
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//
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// Write PADCFG DW0 register``
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//
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mmio_andthenor32(
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(void *)(uint32_t)PCH_PCR_ADDRESS(
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GpioGroupInfo[GroupIndex].Community,
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PadCfgReg),
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~(uint32_t)Dw0RegMask, (uint32_t)Dw0Reg);
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}
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Data32 = read32((void *)PCH_PCR_ADDRESS(
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GpioGroupInfo[GroupIndex].Community, PadCfgReg + 0x4));
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FinalValue = ((Data32 & (~Dw1RegMask)) | Dw1Reg);
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if (Data32 != FinalValue) {
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//
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// Write PADCFG DW1 register
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//
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mmio_andthenor32(
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(void *)(uint32_t)PCH_PCR_ADDRESS(
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GpioGroupInfo[GroupIndex].Community,
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PadCfgReg + 0x4),
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~(uint32_t)Dw1RegMask, (uint32_t)Dw1Reg);
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}
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//
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// Update value to be programmed in HOSTSW_OWN register
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//
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HostSoftOwnRegMask[GroupIndex] |= LShiftU64(
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(uint64_t)GpioData->GpioConfig.HostSoftPadOwn & 0x1,
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PadNumber);
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HostSoftOwnReg[GroupIndex] |= LShiftU64(
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(uint64_t)GpioData->GpioConfig.HostSoftPadOwn >> 0x1,
|
|
PadNumber);
|
|
|
|
//
|
|
// Update value to be programmed in GPI_GPE_EN register
|
|
//
|
|
GpiGpeEnRegMask[GroupIndex] |= LShiftU64(
|
|
(uint64_t)(GpioData->GpioConfig.InterruptConfig & 0x1),
|
|
PadNumber);
|
|
GpiGpeEnReg[GroupIndex] |= LShiftU64(
|
|
(uint64_t)(GpioData->GpioConfig.InterruptConfig &
|
|
GpioIntSci) >>
|
|
3,
|
|
PadNumber);
|
|
}
|
|
|
|
for (Index = 0; Index < NumberOfGroups; Index++) {
|
|
//
|
|
// Write HOSTSW_OWN registers
|
|
//
|
|
if (GpioGroupInfo[Index].HostOwnOffset !=
|
|
NO_REGISTER_FOR_PROPERTY) {
|
|
mmio_andthenor32(
|
|
(void *)PCH_PCR_ADDRESS(
|
|
GpioGroupInfo[Index].Community,
|
|
GpioGroupInfo[Index].HostOwnOffset),
|
|
~(uint32_t)(HostSoftOwnRegMask[Index] &
|
|
0xFFFFFFFF),
|
|
(uint32_t)(HostSoftOwnReg[Index] & 0xFFFFFFFF));
|
|
mmio_andthenor32(
|
|
(void *)PCH_PCR_ADDRESS(
|
|
GpioGroupInfo[Index].Community,
|
|
GpioGroupInfo[Index].HostOwnOffset +
|
|
0x4),
|
|
~(uint32_t)(RShiftU64(HostSoftOwnRegMask[Index],
|
|
32)),
|
|
(uint32_t)(
|
|
RShiftU64(HostSoftOwnReg[Index], 32)));
|
|
}
|
|
|
|
//
|
|
// Write GPI_GPE_EN registers
|
|
//
|
|
if (GpioGroupInfo[Index].GpiGpeEnOffset !=
|
|
NO_REGISTER_FOR_PROPERTY) {
|
|
mmio_andthenor32(
|
|
(void *)PCH_PCR_ADDRESS(
|
|
GpioGroupInfo[Index].Community,
|
|
GpioGroupInfo[Index].GpiGpeEnOffset),
|
|
~(uint32_t)(GpiGpeEnRegMask[Index] &
|
|
0xFFFFFFFF),
|
|
(uint32_t)(GpiGpeEnReg[Index] & 0xFFFFFFFF));
|
|
mmio_andthenor32(
|
|
(void *)PCH_PCR_ADDRESS(
|
|
GpioGroupInfo[Index].Community,
|
|
GpioGroupInfo[Index].GpiGpeEnOffset +
|
|
0x4),
|
|
~(uint32_t)(
|
|
RShiftU64(GpiGpeEnRegMask[Index], 32)),
|
|
(uint32_t)(RShiftU64(GpiGpeEnReg[Index], 32)));
|
|
}
|
|
}
|
|
}
|