67 lines
1.3 KiB
C
67 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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#include <soc/msr.h>
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static const unsigned int cpu_bus_clk_freq_table[] = {
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83333,
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100000,
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133333,
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116666,
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80000,
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93333,
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90000,
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88900,
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87500
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};
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unsigned int cpu_bus_freq_khz(void)
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{
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msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
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if ((clk_info.lo & 0xf) < ARRAY_SIZE(cpu_bus_clk_freq_table))
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return cpu_bus_clk_freq_table[clk_info.lo & 0xf];
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return 0;
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}
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unsigned long tsc_freq_mhz(void)
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{
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msr_t platform_info;
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unsigned int bclk_khz = cpu_bus_freq_khz();
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if (!bclk_khz)
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return 0;
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platform_info = rdmsr(MSR_PLATFORM_INFO);
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return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
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}
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void set_max_freq(void)
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{
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msr_t perf_ctl;
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msr_t msr;
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/* Enable Intel SpeedStep */
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 16);
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wrmsr(IA32_MISC_ENABLE, msr);
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/* Enable Burst Mode */
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.hi = 0;
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wrmsr(IA32_MISC_ENABLE, msr);
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/* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of the PERF_CTL */
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msr = rdmsr(MSR_IACORE_TURBO_RATIOS);
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perf_ctl.lo = (msr.lo & 0x003f0000) >> 8;
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/* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of the PERF_CTL */
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msr = rdmsr(MSR_IACORE_TURBO_VIDS);
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perf_ctl.lo |= (msr.lo & 0x007f0000) >> 16;
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perf_ctl.hi = 0;
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wrmsr(IA32_PERF_CTL, perf_ctl);
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}
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