331 lines
10 KiB
C
331 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acpimmio.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <gpio.h>
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#include <southbridge/amd/pi/hudson/hudson.h>
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#include <southbridge/amd/pi/hudson/pci_devs.h>
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#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <northbridge/amd/pi/00730F01/pci_devs.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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#include <superio/nuvoton/nct5104d/nct5104d.h>
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#include <smbios.h>
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#include <string.h>
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#include <AGESA.h>
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#include "gpio_ftns.h"
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#define SPD_SIZE 128
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#define PM_RTC_CONTROL 0x56
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#define PM_S_STATE_CONTROL 0xBA
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/***********************************************************
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*
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* These values are used by the PCI configuration space,
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* MP Tables. TODO: Make ACPI use these values too.
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*/
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static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
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[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
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/* INTA# - INTH# */
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[0x00] = 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
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/* Misc-nil,0,1,2, INT from Serial irq */
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[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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/* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
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[0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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[0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* IMC INT0 - 5 */
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[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
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[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* USB Devs 18/19/22 INTA-C */
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[0x30] = 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F,
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[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* SATA */
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[0x40] = 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x60] = 0x00,0x00,0x1F
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};
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static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
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[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
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/* INTA# - INTH# */
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[0x00] = 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F,
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/* Misc-nil,0,1,2, INT from Serial irq */
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[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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/* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
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[0x10] = 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x10,
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[0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* IMC INT0 - 5 */
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[0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
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[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* USB Devs 18/19/20/22 INTA-C */
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[0x30] = 0x12,0x1F,0x12,0x1F,0x12,0x1F,0x1F,0x00,
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[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* SATA */
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[0x40] = 0x1F,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x60] = 0x00,0x00,0x1F
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};
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/*
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* This table defines the index into the picr/intr_data
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* tables for each device. Any enabled device and slot
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* that uses hardware interrupts should have an entry
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* in this table to define its index into the FCH
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* PCI_INTR register 0xC00/0xC01. This index will define
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* the interrupt that it should use. Putting PIRQ_A into
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* the PIN A index for a device will tell that device to
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* use PIC IRQ 10 if it uses PIN A for its hardware INT.
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*/
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static const struct pirq_struct mainboard_pirq_data[] = {
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/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
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{GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
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{ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
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{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
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{NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
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{NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
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{XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
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{SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
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{OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
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{EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
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{OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
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{EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
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{SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
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{HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
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{SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
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{OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */
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{EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */
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};
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/* PIRQ Setup */
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static void pirq_setup(void)
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{
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pirq_data_ptr = mainboard_pirq_data;
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pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
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intr_data_ptr = mainboard_intr_data;
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picr_data_ptr = mainboard_picr_data;
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}
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/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit
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* once configuration file format for SPI flash storage is complete.
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*/
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#define SIO_PORT 0x2e
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static void config_gpio_mux(void)
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{
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struct device *uart, *gpio;
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uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
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gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
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if (uart)
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uart->enabled = CONFIG(APU2_PINMUX_UART_C);
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if (gpio)
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gpio->enabled = CONFIG(APU2_PINMUX_GPIO0);
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uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
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gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
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if (uart)
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uart->enabled = CONFIG(APU2_PINMUX_UART_D);
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if (gpio)
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gpio->enabled = CONFIG(APU2_PINMUX_GPIO1);
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}
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/**********************************************
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* enable the dedicated function in mainboard.
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**********************************************/
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#if CONFIG(GENERATE_SMBIOS_TABLES)
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static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle,
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unsigned long *current)
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{
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struct smbios_type16 *t;
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u32 max_capacity;
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int len = 0;
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t = (struct smbios_type16 *)*current;
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len = sizeof(struct smbios_type16);
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memset(t, 0, len);
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max_capacity = get_spd_offset() ? 4 : 2; /* 4GB or 2GB variant */
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t->type = SMBIOS_PHYS_MEMORY_ARRAY;
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t->handle = *handle;
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t->length = len - 2;
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t->type = SMBIOS_PHYS_MEMORY_ARRAY;
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t->use = MEMORY_ARRAY_USE_SYSTEM;
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t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
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t->memory_error_correction = agesa_dmi->T16.MemoryErrorCorrection;
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t->maximum_capacity = max_capacity * 1024 * 1024;
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t->memory_error_information_handle = 0xfffe;
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t->number_of_memory_devices = 1;
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*current += len;
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return len;
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}
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static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle,
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unsigned long *current)
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{
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struct smbios_type17 *t;
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int len;
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t = (struct smbios_type17 *)*current;
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memset(t, 0, sizeof(struct smbios_type17));
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t->type = SMBIOS_MEMORY_DEVICE;
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t->length = sizeof(struct smbios_type17) - 2;
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t->handle = *handle + 1;
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t->phys_memory_array_handle = *handle;
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t->memory_error_information_handle = 0xfffe;
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t->total_width = agesa_dmi->T17[0][0][0].TotalWidth;
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t->data_width = agesa_dmi->T17[0][0][0].DataWidth;
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t->size = agesa_dmi->T17[0][0][0].MemorySize;
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t->form_factor = agesa_dmi->T17[0][0][0].FormFactor;
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t->device_set = agesa_dmi->T17[0][0][0].DeviceSet;
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t->device_locator = smbios_add_string(t->eos,
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agesa_dmi->T17[0][0][0].DeviceLocator);
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t->bank_locator = smbios_add_string(t->eos,
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agesa_dmi->T17[0][0][0].BankLocator);
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t->memory_type = agesa_dmi->T17[0][0][0].MemoryType;
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t->type_detail = *(u16 *)&agesa_dmi->T17[0][0][0].TypeDetail;
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t->speed = agesa_dmi->T17[0][0][0].Speed;
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t->manufacturer = agesa_dmi->T17[0][0][0].ManufacturerIdCode;
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t->serial_number = smbios_add_string(t->eos,
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agesa_dmi->T17[0][0][0].SerialNumber);
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t->part_number = smbios_add_string(t->eos,
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agesa_dmi->T17[0][0][0].PartNumber);
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t->attributes = agesa_dmi->T17[0][0][0].Attributes;
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t->extended_size = agesa_dmi->T17[0][0][0].ExtSize;
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t->clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed;
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t->minimum_voltage = 1500; /* From SPD: 1.5V */
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t->maximum_voltage = 1500;
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len = t->length + smbios_string_table_len(t->eos);
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*current += len;
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return len;
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}
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static int mainboard_smbios_data(struct device *dev, int *handle,
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unsigned long *current)
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{
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DMI_INFO *agesa_dmi;
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int len = 0;
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agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI);
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if (!agesa_dmi)
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return len;
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len += mainboard_smbios_type16(agesa_dmi, handle, current);
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len += mainboard_smbios_type17(agesa_dmi, handle, current);
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*handle += 2;
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return len;
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}
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#endif
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static void mainboard_enable(struct device *dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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config_gpio_mux();
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//
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// Enable the RTC output
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//
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pm_write16(PM_RTC_CONTROL, pm_read16(PM_RTC_CONTROL) | (1 << 11));
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//
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// Enable power on from WAKE#
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//
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pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14));
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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#if CONFIG(GENERATE_SMBIOS_TABLES)
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dev->ops->get_smbios_data = mainboard_smbios_data;
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#endif
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}
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static void mainboard_final(void *chip_info)
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{
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//
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// Turn off LED 2 and LED 3
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//
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gpio_set(GPIO_58, 1);
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gpio_set(GPIO_59, 1);
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}
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/*
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* We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address
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* into the smbios serial number location.
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*/
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const char *smbios_mainboard_serial_number(void)
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{
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static char serial[10];
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struct device *dev;
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uintptr_t bar10;
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u32 mac_addr = 0;
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int i;
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/* Already initialized. */
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if (serial[0] != 0)
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return serial;
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dev = pcidev_on_root(2, 2);
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if (dev)
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dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0));
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if (!dev)
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return serial;
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/* Read in the last 3 bytes of NIC's MAC address. */
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bar10 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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bar10 &= 0xFFFE0000;
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bar10 += 0x5400;
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for (i = 3; i < 6; i++) {
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mac_addr <<= 8;
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mac_addr |= read8((u8 *)bar10 + i);
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}
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mac_addr &= 0x00FFFFFF;
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mac_addr /= 4;
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mac_addr -= 64;
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snprintf(serial, sizeof(serial), "%d", mac_addr);
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return serial;
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}
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/*
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* We will stuff the memory size into the smbios sku location.
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*/
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const char *smbios_system_sku(void)
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{
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static char sku[5];
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if (sku[0] != 0)
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return sku;
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if (!get_spd_offset())
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snprintf(sku, sizeof(sku), "2 GB");
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else
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snprintf(sku, sizeof(sku), "4 GB");
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return sku;
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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.final = mainboard_final,
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};
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