138 lines
5.3 KiB
C
138 lines
5.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acpimmio.h>
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#include <device/mmio.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
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#include <southbridge/amd/cimx/sb800/pci_devs.h>
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#include <northbridge/amd/agesa/family14/pci_devs.h>
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/***********************************************************
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*
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* These values are used by the PCI configuration space,
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* MP Tables. TODO: Make ACPI use these values too.
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*
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* The Persimmon PCI INTA/B/C/D pins are connected to
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* FCH pins INTE/F/G/H on the schematic so these need
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* to be routed as well.
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*/
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static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
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/* INTA# - INTH# */
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[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
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/* Misc-nil,0,1,2, INT from Serial irq */
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[0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
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[0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
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/* IMC INT0 - 5 */
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[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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/* USB Devs 18/19/20/22 INTA-C */
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[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
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/* IDE, SATA */
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[0x40] = 0x0B,0x0B,
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/* GPPInt0 - 3 */
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[0x50] = 0x0A,0x0B,0x0A,0x0B
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};
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static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
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/* INTA# - INTH# */
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[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
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/* Misc-nil,0,1,2, INT from Serial irq */
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[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
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[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
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/* IMC INT0 - 5 */
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[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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/* USB Devs 18/19/22/20 INTA-C */
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[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
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/* IDE, SATA */
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[0x40] = 0x11,0x13,
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/* GPPInt0 - 3 */
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[0x50] = 0x10,0x11,0x12,0x13
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};
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/*
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* This table defines the index into the picr/intr_data
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* tables for each device. Any enabled device and slot
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* that uses hardware interrupts should have an entry
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* in this table to define its index into the FCH
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* PCI_INTR register 0xC00/0xC01. This index will define
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* the interrupt that it should use. Putting PIRQ_A into
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* the PIN A index for a device will tell that device to
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* use PIC IRQ 10 if it uses PIN A for its hardware INT.
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*/
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/*
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* Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
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* but because PCI INT_PIN swizzling isn't implemented to match
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* the IDSEL (dev 3) of the slot, the table is adjusted for the
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* swizzle and INTA is connected to PIRQH so PINA/B/C/D on
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* off-chip devices should get mapped to PIRQH/E/F/G.
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*/
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static const struct pirq_struct mainboard_pirq_data[] = {
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/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
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{GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
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{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */
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{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */
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{SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
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{OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
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{EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
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{OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
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{EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
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{SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
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{IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */
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{HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
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{SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */
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{OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */
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{OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */
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{EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */
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};
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/* PIRQ Setup */
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static void pirq_setup(void)
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{
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pirq_data_ptr = mainboard_pirq_data;
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pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
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intr_data_ptr = mainboard_intr_data;
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picr_data_ptr = mainboard_picr_data;
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}
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/**********************************************
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* Enable the dedicated functions of the board.
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**********************************************/
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static void mainboard_enable(struct device *dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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/* enable GPP CLK0 thru CLK3 (interleaved) */
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/* disable GPP CLK4 thru SLT_GFX_CLK */
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misc_write8(0, 0xff);
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misc_write8(1, 0xff);
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misc_write8(2, 0);
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misc_write8(3, 0);
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misc_write8(4, 0);
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/*
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* Initialize ASF registers to an arbitrary address because someone
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* long ago set things up this way inside the SPD read code. The
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* SPD read code has been made generic and moved out of the board
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* directory, so the ASF init is being done here.
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*/
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pm_write8(0x29, 0x80);
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pm_write8(0x28, 0x61);
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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