93 lines
3.5 KiB
C
93 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <southbridge/amd/agesa/hudson/pci_devs.h>
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#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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#include <northbridge/amd/agesa/family16kb/pci_devs.h>
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static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
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/* INTA# - INTH# */
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[0x00] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
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/* Misc-nil,0,1,2, INT from Serial irq */
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[0x08] = 0x5A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
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[0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
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/* IMC INT0 - 5 */
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[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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/* USB Devs 18/19/22 INTA-B */
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[0x30] = 0x05,0x04,0x05,0x04,0x05,0x04,0x1F,0x1F,
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/* RSVD, SATA */
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[0x40] = 0x1F, 0x07
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};
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static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
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/* INTA# - INTH# */
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[0x00] = 0x10,0x11,0x12,0x13,0x1F,0x1F,0x1F,0x1F,
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/* Misc-nil,0,1,2, INT from Serial irq */
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[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
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[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x1F,
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/* IMC INT0 - 5 */
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[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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/* USB Devs 18/19/22 INTA-B */
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[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x1F,0x1F,
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/* RSVD, SATA */
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[0x40] = 0x1F, 0x13
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};
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/*
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* This table defines the index into the picr/intr_data
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* tables for each device. Any enabled device and slot
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* that uses hardware interrupts should have an entry
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* in this table to define its index into the FCH
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* PCI_INTR register 0xC00/0xC01. This index will define
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* the interrupt that it should use. Putting PIRQ_A into
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* the PIN A index for a device will tell that device to
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* use PIC IRQ 10 if it uses PIN A for its hardware INT.
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*/
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static const struct pirq_struct mainboard_pirq_data[] = {
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/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
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{GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
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{ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
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{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
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{NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* Edge: 02.5 */
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{XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
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{SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
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{OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
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{EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
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{OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
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{EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
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{OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */
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{EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */
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{HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
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};
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const u8 *picr_data = mainboard_picr_data;
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const u8 *intr_data = mainboard_intr_data;
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/* PIRQ Setup */
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static void pirq_setup(void)
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{
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pirq_data_ptr = mainboard_pirq_data;
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pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
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intr_data_ptr = mainboard_intr_data;
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picr_data_ptr = mainboard_picr_data;
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}
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/**********************************************
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* enable the dedicated function in mainboard.
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**********************************************/
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static void mainboard_enable(struct device *dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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