359 lines
8.9 KiB
C
359 lines
8.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <boot/coreboot_tables.h>
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#include <console/console.h>
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#include <cpu/cpu.h>
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#include <post.h>
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#include <string.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/tsc.h>
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#include <device/path.h>
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#include <device/device.h>
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#include <smp/spinlock.h>
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#ifndef __x86_64__
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(uint32_t flag)
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{
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uint32_t f1, f2;
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asm(
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"pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl\n\t"
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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return ((f1^f2) & flag) != 0;
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}
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/*
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* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
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* by the fact that they preserve the flags across the division of 5/2.
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* PII and PPro exhibit this behavior too, but they have cpuid available.
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*/
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/*
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* Perform the Cyrix 5/2 test. A Cyrix won't change
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* the flags, while other 486 chips will.
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*/
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static inline int test_cyrix_52div(void)
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{
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unsigned int test;
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__asm__ __volatile__(
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"sahf\n\t" /* clear flags (%eax = 0x0005) */
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"div %b2\n\t" /* divide 5 by 2 */
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"lahf" /* store flags into %ah */
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: "=a" (test)
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: "0" (5), "q" (2)
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: "cc");
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/* AH is 0x02 on Cyrix after the divide.. */
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return (unsigned char) (test >> 8) == 0x02;
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}
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/*
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* Detect a NexGen CPU running without BIOS hypercode new enough
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* to have CPUID. (Thanks to Herbert Oppmann)
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*/
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static int deep_magic_nexgen_probe(void)
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{
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int ret;
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__asm__ __volatile__ (
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" movw $0x5555, %%ax\n"
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" xorw %%dx,%%dx\n"
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" movw $2, %%cx\n"
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" divw %%cx\n"
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" movl $0, %%eax\n"
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" jnz 1f\n"
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" movl $1, %%eax\n"
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"1:\n"
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: "=a" (ret) : : "cx", "dx");
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return ret;
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}
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#endif
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/* List of CPU vendor strings along with their normalized
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* id values.
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*/
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static struct {
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int vendor;
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const char *name;
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} x86_vendors[] = {
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{ X86_VENDOR_INTEL, "GenuineIntel", },
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{ X86_VENDOR_CYRIX, "CyrixInstead", },
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{ X86_VENDOR_AMD, "AuthenticAMD", },
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{ X86_VENDOR_UMC, "UMC UMC UMC ", },
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{ X86_VENDOR_NEXGEN, "NexGenDriven", },
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{ X86_VENDOR_CENTAUR, "CentaurHauls", },
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{ X86_VENDOR_RISE, "RiseRiseRise", },
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{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
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{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
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{ X86_VENDOR_NSC, "Geode by NSC", },
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{ X86_VENDOR_SIS, "SiS SiS SiS ", },
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{ X86_VENDOR_HYGON, "HygonGenuine", },
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};
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static const char *const x86_vendor_name[] = {
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[X86_VENDOR_INTEL] = "Intel",
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[X86_VENDOR_CYRIX] = "Cyrix",
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[X86_VENDOR_AMD] = "AMD",
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[X86_VENDOR_UMC] = "UMC",
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[X86_VENDOR_NEXGEN] = "NexGen",
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[X86_VENDOR_CENTAUR] = "Centaur",
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[X86_VENDOR_RISE] = "Rise",
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[X86_VENDOR_TRANSMETA] = "Transmeta",
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[X86_VENDOR_NSC] = "NSC",
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[X86_VENDOR_SIS] = "SiS",
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[X86_VENDOR_HYGON] = "Hygon",
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};
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static const char *cpu_vendor_name(int vendor)
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{
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const char *name;
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name = "<invalid CPU vendor>";
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if ((vendor < ARRAY_SIZE(x86_vendor_name)) &&
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(x86_vendor_name[vendor] != 0))
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name = x86_vendor_name[vendor];
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return name;
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}
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static void identify_cpu(struct device *cpu)
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{
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char vendor_name[16];
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int i;
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vendor_name[0] = '\0'; /* Unset */
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#ifndef __x86_64__
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/* Find the id and vendor_name */
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if (!cpu_have_cpuid()) {
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/* Its a 486 if we can modify the AC flag */
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if (flag_is_changeable_p(X86_EFLAGS_AC))
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cpu->device = 0x00000400; /* 486 */
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else
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cpu->device = 0x00000300; /* 386 */
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if ((cpu->device == 0x00000400) && test_cyrix_52div())
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memcpy(vendor_name, "CyrixInstead", 13);
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/* If we ever care we can enable cpuid here */
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/* Detect NexGen with old hypercode */
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else if (deep_magic_nexgen_probe())
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memcpy(vendor_name, "NexGenDriven", 13);
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}
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#endif
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if (cpu_have_cpuid()) {
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int cpuid_level;
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struct cpuid_result result;
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result = cpuid(0x00000000);
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cpuid_level = result.eax;
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vendor_name[0] = (result.ebx >> 0) & 0xff;
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vendor_name[1] = (result.ebx >> 8) & 0xff;
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vendor_name[2] = (result.ebx >> 16) & 0xff;
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vendor_name[3] = (result.ebx >> 24) & 0xff;
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vendor_name[4] = (result.edx >> 0) & 0xff;
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vendor_name[5] = (result.edx >> 8) & 0xff;
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vendor_name[6] = (result.edx >> 16) & 0xff;
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vendor_name[7] = (result.edx >> 24) & 0xff;
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vendor_name[8] = (result.ecx >> 0) & 0xff;
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vendor_name[9] = (result.ecx >> 8) & 0xff;
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vendor_name[10] = (result.ecx >> 16) & 0xff;
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vendor_name[11] = (result.ecx >> 24) & 0xff;
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vendor_name[12] = '\0';
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/* Intel-defined flags: level 0x00000001 */
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if (cpuid_level >= 0x00000001)
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cpu->device = cpu_get_cpuid();
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else
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/* Have CPUID level 0 only unheard of */
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cpu->device = 0x00000400;
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}
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cpu->vendor = X86_VENDOR_UNKNOWN;
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for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
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if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
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cpu->vendor = x86_vendors[i].vendor;
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break;
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}
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}
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}
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struct cpu_driver *find_cpu_driver(struct device *cpu)
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{
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struct cpu_driver *driver;
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for (driver = _cpu_drivers; driver < _ecpu_drivers; driver++) {
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const struct cpu_device_id *id;
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for (id = driver->id_table;
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id->vendor != X86_VENDOR_INVALID; id++) {
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if ((cpu->vendor == id->vendor) &&
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(cpu->device == id->device))
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return driver;
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if (id->vendor == X86_VENDOR_ANY)
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return driver;
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}
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}
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return NULL;
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}
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static void set_cpu_ops(struct device *cpu)
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{
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struct cpu_driver *driver = find_cpu_driver(cpu);
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cpu->ops = driver ? driver->ops : NULL;
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}
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/* Keep track of default APIC ids for SMM. */
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static int cpus_default_apic_id[CONFIG_MAX_CPUS];
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/*
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* When CPUID executes with EAX set to 1, additional processor identification
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* information is returned to EBX register:
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* Default APIC ID: EBX[31-24] - this number is the 8 bit ID that is assigned
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* to the local APIC on the processor during power on.
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*/
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static int initial_lapicid(void)
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{
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return cpuid_ebx(1) >> 24;
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}
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/* Function to keep track of cpu default apic_id */
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void cpu_add_map_entry(unsigned int index)
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{
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cpus_default_apic_id[index] = initial_lapicid();
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}
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/* Returns default APIC id based on logical_cpu number or < 0 on failure. */
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int cpu_get_apic_id(int logical_cpu)
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{
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if (logical_cpu >= CONFIG_MAX_CPUS || logical_cpu < 0)
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return -1;
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return cpus_default_apic_id[logical_cpu];
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}
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void cpu_initialize(unsigned int index)
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{
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/* Because we busy wait at the printk spinlock.
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* It is important to keep the number of printed messages
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* from secondary cpus to a minimum, when debugging is
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* disabled.
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*/
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struct device *cpu;
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struct cpu_info *info;
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struct cpuinfo_x86 c;
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info = cpu_info();
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printk(BIOS_INFO, "Initializing CPU #%d\n", index);
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cpu = info->cpu;
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if (!cpu)
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die("CPU: missing CPU device structure");
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if (cpu->initialized)
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return;
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post_log_path(cpu);
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/* Find what type of CPU we are dealing with */
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identify_cpu(cpu);
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printk(BIOS_DEBUG, "CPU: vendor %s device %x\n",
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cpu_vendor_name(cpu->vendor), cpu->device);
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get_fms(&c, cpu->device);
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printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n",
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c.x86, c.x86_model, c.x86_mask);
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/* Lookup the cpu's operations */
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set_cpu_ops(cpu);
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if (!cpu->ops) {
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/* mask out the stepping and try again */
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cpu->device -= c.x86_mask;
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set_cpu_ops(cpu);
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cpu->device += c.x86_mask;
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if (!cpu->ops)
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die("Unknown cpu");
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printk(BIOS_DEBUG, "Using generic CPU ops (good)\n");
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}
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/* Initialize the CPU */
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if (cpu->ops && cpu->ops->init) {
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cpu->enabled = 1;
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cpu->initialized = 1;
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cpu->ops->init(cpu);
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}
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post_log_clear();
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printk(BIOS_INFO, "CPU #%d initialized\n", index);
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}
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void lb_arch_add_records(struct lb_header *header)
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{
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uint32_t freq_khz;
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struct lb_tsc_info *tsc_info;
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/* Don't advertise a TSC rate unless it's constant. */
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if (!tsc_constant_rate())
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return;
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freq_khz = tsc_freq_mhz() * 1000;
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/* No use exposing a TSC frequency that is zero. */
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if (freq_khz == 0)
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return;
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tsc_info = (void *)lb_new_record(header);
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tsc_info->tag = LB_TAG_TSC_INFO;
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tsc_info->size = sizeof(*tsc_info);
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tsc_info->freq_khz = freq_khz;
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}
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void arch_bootstate_coreboot_exit(void)
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{
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/* APs are already parked by existing infrastructure. */
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if (!CONFIG(PARALLEL_MP_AP_WORK))
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return;
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/* APs are waiting for work. Last thing to do is park them. */
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mp_park_aps();
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}
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/*
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* Previously cpu_index() implementation assumes that cpu_index()
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* function will always getting called from coreboot context
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* (ESP stack pointer will always refer to coreboot).
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*
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* But with MP_SERVICES_PPI implementation in coreboot this
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* assumption might not be true, where FSP context (stack pointer refers
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* to FSP) will request to get cpu_index().
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*
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* Hence new logic to use cpuid to fetch lapic id and matches with
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* cpus_default_apic_id[] variable to return correct cpu_index().
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*/
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int cpu_index(void)
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{
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int i;
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int lapic_id = initial_lapicid();
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for (i = 0; i < CONFIG_MAX_CPUS; i++) {
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if (cpu_get_apic_id(i) == lapic_id)
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return i;
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}
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return -1;
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}
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uintptr_t cpu_get_lapic_addr(void)
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{
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return LOCAL_APIC_ADDR;
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}
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