578 lines
14 KiB
Plaintext
578 lines
14 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config SOC_AMD_PICASSO
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bool
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help
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AMD Picasso support
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if SOC_AMD_PICASSO
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select RESET_VECTOR_IN_RAM
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select X86_AMD_FIXED_MTRRS
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select X86_AMD_INIT_SIPI
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select ACPI_AMD_HARDWARE_SLEEP_VALUES
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select DRIVERS_I2C_DESIGNWARE
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select DRIVERS_USB_PCI_XHCI
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select GENERIC_GPIO_LIB
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select IDT_IN_EVERY_STAGE
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select IOAPIC
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select HAVE_EM100_SUPPORT
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select HAVE_USBDEBUG_OPTIONS
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select TSC_MONOTONIC_TIMER
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select SOC_AMD_COMMON_BLOCK_SPI
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select TSC_SYNC_LFENCE
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select UDELAY_TSC
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select SOC_AMD_COMMON
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select SOC_AMD_COMMON_BLOCK
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select SOC_AMD_COMMON_BLOCK_HAS_ESPI
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select SOC_AMD_COMMON_BLOCK_IOMMU
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select SOC_AMD_COMMON_BLOCK_ACPIMMIO
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select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
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select SOC_AMD_COMMON_BLOCK_ACPI
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select SOC_AMD_COMMON_BLOCK_GRAPHICS
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select SOC_AMD_COMMON_BLOCK_LPC
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_HDA
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select SOC_AMD_COMMON_BLOCK_SATA
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select SOC_AMD_COMMON_BLOCK_SMBUS
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2
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select PROVIDES_ROM_SHARING
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select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select HAVE_SMI_HANDLER
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select SSE2
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select RTC
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select PLATFORM_USES_FSP2_0
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select FSP_COMPRESS_FSP_M_LZMA
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select FSP_COMPRESS_FSP_S_LZMA
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select UDK_2017_BINDING
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select HAVE_CF9_RESET
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select SUPPORT_CPU_UCODE_IN_CBFS
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select ACPI_NO_SMI_GNVS
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config MEMLAYOUT_LD_FILE
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string
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default "src/soc/amd/picasso/memlayout.ld"
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config EARLY_RESERVED_DRAM_BASE
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hex
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default 0x2000000
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help
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This variable defines the base address of the DRAM which is reserved
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for usage by coreboot in early stages (i.e. before ramstage is up).
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This memory gets reserved in BIOS tables to ensure that the OS does
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not use it, thus preventing corruption of OS memory in case of S3
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resume.
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config EARLYRAM_BSP_STACK_SIZE
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hex
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default 0x1000
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config PSP_APOB_DRAM_ADDRESS
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hex
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default 0x2001000
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help
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Location in DRAM where the PSP will copy the AGESA PSP Output
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Block.
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config PSP_SHAREDMEM_BASE
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hex
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default 0x2011000 if VBOOT
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default 0x0
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help
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This variable defines the base address in DRAM memory where PSP copies
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vboot workbuf to. This is used in linker script to have a static
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allocation for the buffer as well as for adding relevant entries in
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BIOS directory table for the PSP.
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config PSP_SHAREDMEM_SIZE
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hex
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default 0x8000 if VBOOT
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default 0x0
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help
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Sets the maximum size for the PSP to pass the vboot workbuf and
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any logs or timestamps back to coreboot. This will be copied
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into main memory by the PSP and will be available when the x86 is
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started. The workbuf's base depends on the address of the reset
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vector.
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0x1600
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help
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Increase this value if preram cbmem console is getting truncated
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config BOOTBLOCK_ADDR
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hex
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default 0x2030000
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help
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Sets the address in DRAM where bootblock should be loaded.
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0x10000
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help
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Sets the size of the bootblock stage that should be loaded in DRAM.
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This variable controls the DRAM allocation size in linker script
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for bootblock stage.
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config X86_RESET_VECTOR
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hex
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depends on ARCH_X86
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default 0x203fff0
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help
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Sets the reset vector within bootblock where x86 starts execution.
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Reset vector is supposed to live at offset -0x10 from end of
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bootblock i.e. BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10.
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config ROMSTAGE_ADDR
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hex
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default 0x2040000
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help
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Sets the address in DRAM where romstage should be loaded.
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config ROMSTAGE_SIZE
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hex
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default 0x80000
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help
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Sets the size of DRAM allocation for romstage in linker script.
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config FSP_M_ADDR
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hex
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default 0x20C0000
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help
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Sets the address in DRAM where FSP-M should be loaded. cbfstool
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performs relocation of FSP-M to this address.
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config FSP_M_SIZE
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hex
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default 0x80000
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help
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Sets the size of DRAM allocation for FSP-M in linker script.
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config VERSTAGE_ADDR
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hex
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depends on VBOOT_SEPARATE_VERSTAGE
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default 0x2140000
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help
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Sets the address in DRAM where verstage should be loaded if running
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as a separate stage on x86.
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config VERSTAGE_SIZE
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hex
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depends on VBOOT_SEPARATE_VERSTAGE
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default 0x80000
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help
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Sets the size of DRAM allocation for verstage in linker script if
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running as a separate stage on x86.
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config RAMBASE
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hex
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default 0x10000000
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config CPU_ADDR_BITS
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int
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default 48
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config MMCONF_BASE_ADDRESS
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hex
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default 0xF8000000
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config MMCONF_BUS_NUMBER
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int
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default 64
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config VERSTAGE_ADDR
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hex
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default 0x4000000
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config VGA_BIOS_ID
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string
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default "1002,15d8,c1"
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help
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The default VGA BIOS PCI vendor/device ID should be set to the
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result of the map_oprom_vendev_rev() function in northbridge.c.
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config VGA_BIOS_FILE
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string
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default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin"
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config VGA_BIOS_SECOND
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def_bool y
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config VGA_BIOS_SECOND_ID
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string
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default "1002,15dd,c4"
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help
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Because Dali and Picasso need different video BIOSes, but have the
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same vendor/device IDs, we need an alternate method to determine the
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correct video BIOS. In map_oprom_vendev_rev(), we look at the cpuid
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and decide which rom to load.
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Even though the hardware has the same vendor/device IDs, the vBIOS
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contains a *different* device ID, confusing the situation even more.
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config VGA_BIOS_SECOND_FILE
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string
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default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin"
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config CHECK_REV_IN_OPROM_NAME
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bool
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default y
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help
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Select this in the platform BIOS or chipset if the option rom has a
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revision that needs to be checked when searching CBFS.
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config S3_VGA_ROM_RUN
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bool
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default n
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config HEAP_SIZE
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hex
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default 0xc0000
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config EHCI_BAR
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hex
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default 0xfef00000
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config PICASSO_FCH_IOAPIC_ID
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hex
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default 0x8
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help
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The Picasso APU has two IOAPICs, one in the FCH and one in the
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northbridge. Set this value for the intended ID to assign to the
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FCH IOAPIC. The value should be >= MAX_CPUS and different from
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the GNB's IOAPIC_ID.
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config PICASSO_GNB_IOAPIC_ID
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hex
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default 0x9
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help
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The Picasso APU has two IOAPICs, one in the FCH and one in the
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northbridge. Set this value for the intended ID to assign to the
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GNB IOAPIC. The value should be >= MAX_CPUS and different from
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the FCH's IOAPIC_ID.
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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help
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Set this option to y for serial IRQ in continuous mode.
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Otherwise it is in quiet mode.
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config PICASSO_ACPI_IO_BASE
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hex
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default 0x400
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help
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Base address for the ACPI registers.
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config PICASSO_CONSOLE_UART
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bool "Use Picasso UART controller for console"
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default n
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select DRIVERS_UART_8250MEM
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select DRIVERS_UART_8250MEM_32
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select NO_UART_ON_SUPERIO
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select UART_OVERRIDE_REFCLK
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help
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There are four memory-mapped UARTs controllers in Picasso at:
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0: 0xfedc9000
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1: 0xfedca000
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2: 0xfedc3000
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3: 0xfedcf000
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choice
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prompt "UART Frequency"
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depends on PICASSO_CONSOLE_UART
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default PICASSO_UART_48MZ
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config PICASSO_UART_48MZ
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bool "48 MHz clock"
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help
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Select this option for the most compatibility.
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config PICASSO_UART_1_8MZ
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bool "1.8432 MHz clock"
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help
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Select this option if an old payload or Linux ttyS0 arguments
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require it.
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endchoice
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config PICASSO_UART_LEGACY
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bool "Decode legacy I/O range"
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help
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Assign I/O 3F8, 2F8, etc. to a Picasso UART. A UART accessed with I/O
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does not allow all the features of MMIO. The MMIO decode is still
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present when this option is used.
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config CONSOLE_UART_BASE_ADDRESS
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depends on CONSOLE_SERIAL && PICASSO_CONSOLE_UART
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hex
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default 0xfedc9000 if UART_FOR_CONSOLE = 0
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default 0xfedca000 if UART_FOR_CONSOLE = 1
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default 0xfedc3000 if UART_FOR_CONSOLE = 2
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default 0xfedcf000 if UART_FOR_CONSOLE = 3
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config SMM_TSEG_SIZE
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hex
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default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
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default 0x0
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config SMM_RESERVED_SIZE
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hex
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default 0x180000
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config SMM_MODULE_STACK_SIZE
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hex
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default 0x800
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config ACPI_CPU_STRING
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string
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default "\\_SB.C%03d"
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config ACPI_BERT
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bool "Build ACPI BERT Table"
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default y
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depends on HAVE_ACPI_TABLES
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help
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Report Machine Check errors identified in POST to the OS in an
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ACPI Boot Error Record Table.
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config ACPI_BERT_SIZE
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hex
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default 0x4000 if ACPI_BERT
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default 0x0
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help
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Specify the amount of DRAM reserved for gathering the data used to
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generate the ACPI table.
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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select ALWAYS_LOAD_OPROM
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select ALWAYS_RUN_OPROM
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config RO_REGION_ONLY
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string
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depends on CHROMEOS
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default "apu/amdfw"
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config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default 150
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config PICASSO_LPC_IOMUX
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bool
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help
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Picasso's LPC bus signals are MUXed with some of the EMMC signals.
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Select this option if LPC signals are required.
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config DISABLE_SPI_FLASH_ROM_SHARING
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def_bool n
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help
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Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
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which indicates a board level ROM transaction request. This
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removes arbitration with board and assumes the chipset controls
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the SPI flash bus entirely.
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config MAINBOARD_POWER_RESTORE
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def_bool n
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help
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This option determines what state to go to once power is restored
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after having been lost in S0. Select this option to automatically
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return to S0. Otherwise the system will remain in S5 once power
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is restored.
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config FSP_TEMP_RAM_SIZE
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hex
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default 0x40000
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help
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The amount of coreboot-allocated heap and stack usage by the FSP.
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menu "PSP Configuration Options"
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config AMDFW_OUTSIDE_CBFS
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bool
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default n
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help
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The AMDFW (PSP) is typically locatable in cbfs. Select this
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option to manually attach the generated amdfw.rom outside of
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cbfs. The location is selected by the FWM position.
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config AMD_FWM_POSITION_INDEX
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int "Firmware Directory Table location (0 to 5)"
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range 0 5
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default 0 if BOARD_ROMSIZE_KB_512
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default 1 if BOARD_ROMSIZE_KB_1024
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default 2 if BOARD_ROMSIZE_KB_2048
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default 3 if BOARD_ROMSIZE_KB_4096
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default 4 if BOARD_ROMSIZE_KB_8192
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default 5 if BOARD_ROMSIZE_KB_16384
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help
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Typically this is calculated by the ROM size, but there may
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be situations where you want to put the firmware directory
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table in a different location.
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0: 512 KB - 0xFFFA0000
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1: 1 MB - 0xFFF20000
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2: 2 MB - 0xFFE20000
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3: 4 MB - 0xFFC20000
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4: 8 MB - 0xFF820000
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5: 16 MB - 0xFF020000
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comment "AMD Firmware Directory Table set to location for 512KB ROM"
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depends on AMD_FWM_POSITION_INDEX = 0
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comment "AMD Firmware Directory Table set to location for 1MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 1
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comment "AMD Firmware Directory Table set to location for 2MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 2
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comment "AMD Firmware Directory Table set to location for 4MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 3
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comment "AMD Firmware Directory Table set to location for 8MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 4
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comment "AMD Firmware Directory Table set to location for 16MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 5
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config AMD_PUBKEY_FILE
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string
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default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin"
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config USE_PSPSECUREOS
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bool
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default y
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help
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Include the PspSecureOs and PspTrustlet binaries in the PSP build.
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If unsure, answer 'y'
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config PSP_LOAD_MP2_FW
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bool
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default n
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help
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Include the MP2 firmwares and configuration into the PSP build.
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If unsure, answer 'n'
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config PSP_LOAD_S0I3_FW
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bool
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default n
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help
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Select this item to include the S0i3 file into the PSP build.
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config HAVE_PSP_WHITELIST_FILE
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bool "Include a debug whitelist file in PSP build"
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default n
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help
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Support secured unlock prior to reset using a whitelisted
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number? This feature requires a signed whitelist image and
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bootloader from AMD.
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If unsure, answer 'n'
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config PSP_WHITELIST_FILE
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string "Debug whitelist file path"
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depends on HAVE_PSP_WHITELIST_FILE
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default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin"
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config PSP_BOOTLOADER_FILE
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string "Specify the PSP Bootloader file path"
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default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_WL_RV.sbin" if HAVE_PSP_WHITELIST_FILE
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default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin"
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help
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Supply the name of the PSP bootloader file.
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Note that this option may conflict with the whitelist file if a
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different PSP bootloader binary is specified.
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config PSP_SHAREDMEM_SIZE
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hex "Maximum size of shared memory area"
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default 0x3000 if VBOOT
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default 0x0
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help
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Sets the maximum size for the PSP to pass the vboot workbuf and
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any logs or timestamps back to coreboot. This will be copied
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into main memory by the PSP and will be available when the x86 is
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started.
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config PSP_UNLOCK_SECURE_DEBUG
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bool "Unlock secure debug"
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default n
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help
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Select this item to enable secure debug options in PSP.
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config PSP_VERSTAGE_FILE
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string "Specify the PSP_verstage file path"
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depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
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default "$(obj)/psp_verstage.bin"
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help
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Add psp_verstage file to the build & PSP Directory Table
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config PSP_VERSTAGE_SIGNING_TOKEN
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string "Specify the PSP_verstage Signature Token file path"
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depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
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default ""
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help
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Add psp_verstage signature token to the build & PSP Directory Table
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endmenu
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config VBOOT
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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config VBOOT_STARTS_BEFORE_BOOTBLOCK
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def_bool n
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depends on VBOOT
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select ARCH_VERSTAGE_ARMV7
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help
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Runs verstage on the PSP. Only available on
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certain Chrome OS branded parts from AMD.
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config CMOS_RECOVERY_BYTE
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hex
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default 0x51
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depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
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help
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If the workbuf is not passed from the PSP to coreboot, set the
|
|
recovery flag and reboot. The PSP will read this byte, mark the
|
|
recovery request in VBNV, and reset the system into recovery mode.
|
|
|
|
This is the byte before the default first byte used by VBNV
|
|
(0x26 + 0x0E - 1)
|
|
|
|
if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
|
|
|
|
config RWA_REGION_ONLY
|
|
string
|
|
default "apu/amdfw_a"
|
|
help
|
|
Add a space-delimited list of filenames that should only be in the
|
|
RW-A section.
|
|
|
|
config RWB_REGION_ONLY
|
|
string
|
|
default "apu/amdfw_b"
|
|
help
|
|
Add a space-delimited list of filenames that should only be in the
|
|
RW-B section.
|
|
|
|
config PICASSO_FW_A_POSITION
|
|
hex
|
|
help
|
|
Location of the AMD firmware in the RW_A region
|
|
|
|
config PICASSO_FW_B_POSITION
|
|
hex
|
|
help
|
|
Location of the AMD firmware in the RW_B region
|
|
|
|
endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
|
|
|
|
endif # SOC_AMD_PICASSO
|