230 lines
7.3 KiB
C
230 lines
7.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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#include <fsp/util.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/pcie_rp.h>
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#include <soc/gpio_soc_defs.h>
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#include <soc/iomap.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/pcie.h>
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#include <soc/romstage.h>
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#include <soc/soc_chip.h>
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#include <string.h>
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#define FSP_CLK_NOTUSED 0xFF
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#define FSP_CLK_LAN 0x70
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#define FSP_CLK_FREE_RUNNING 0x80
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#define CPU_PCIE_BASE 0x40
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enum pcie_rp_type {
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PCH_PCIE_RP,
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CPU_PCIE_RP,
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};
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static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number)
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{
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assert(type == PCH_PCIE_RP || type == CPU_PCIE_RP);
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if (type == PCH_PCIE_RP)
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return rp_number;
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else // type == CPU_PCIE_RP
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return CPU_PCIE_BASE + rp_number;
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}
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static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_type type,
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const struct pcie_rp_config *cfg, size_t cfg_count)
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{
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size_t i;
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for (i = 0; i < cfg_count; i++) {
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if (!(en_mask & BIT(i)))
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continue;
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if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
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continue;
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if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED))
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m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
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m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i);
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}
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}
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static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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const struct device *dev;
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unsigned int i;
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dev = pcidev_path_on_root(SA_DEVFN_IGD);
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if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev))
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m_cfg->InternalGfx = 1;
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else
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m_cfg->InternalGfx = 0;
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/* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */
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m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? IGD_SM_60MB : 0;
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m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
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m_cfg->SaGv = config->SaGv;
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m_cfg->RMT = config->RMT;
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/* CpuRatio Settings */
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if (config->cpu_ratio_override)
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m_cfg->CpuRatio = config->cpu_ratio_override;
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else
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/* Set CpuRatio to match existing MSR value */
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m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff;
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m_cfg->PrmrrSize = get_valid_prmrr_size();
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m_cfg->EnableC6Dram = config->enable_c6dram;
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/* Disable BIOS Guard */
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m_cfg->BiosGuard = 0;
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/* UART Debug Log */
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m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
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DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO;
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if (CONFIG(DRIVERS_UART_8250IO))
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m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8;
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m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit;
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m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
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/* DP port config */
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m_cfg->DdiPortAConfig = config->DdiPortAConfig;
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m_cfg->DdiPortBConfig = config->DdiPortBConfig;
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m_cfg->DdiPortAHpd = config->DdiPortAHpd;
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m_cfg->DdiPortBHpd = config->DdiPortBHpd;
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m_cfg->DdiPortCHpd = config->DdiPortCHpd;
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m_cfg->DdiPort1Hpd = config->DdiPort1Hpd;
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m_cfg->DdiPort2Hpd = config->DdiPort2Hpd;
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m_cfg->DdiPort3Hpd = config->DdiPort3Hpd;
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m_cfg->DdiPort4Hpd = config->DdiPort4Hpd;
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m_cfg->DdiPortADdc = config->DdiPortADdc;
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m_cfg->DdiPortBDdc = config->DdiPortBDdc;
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m_cfg->DdiPortCDdc = config->DdiPortCDdc;
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m_cfg->DdiPort1Ddc = config->DdiPort1Ddc;
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m_cfg->DdiPort2Ddc = config->DdiPort2Ddc;
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m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
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m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
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/* Image clock: disable all clocks for bypassing FSP pin mux */
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memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
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/* Enable Hyper Threading */
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m_cfg->HyperThreading = 1;
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/* Disable Lock PCU Thermal Management registers */
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m_cfg->LockPTMregs = 0;
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/* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */
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m_cfg->ChHashMask = 0x30CC;
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/* Enable SMBus controller */
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dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
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m_cfg->SmbusEnable = is_dev_enabled(dev);
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/* Set debug probe type */
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m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
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/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
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dev = pcidev_path_on_root(PCH_DEVFN_HDA);
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m_cfg->PchHdaEnable = is_dev_enabled(dev);
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m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
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/*
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* All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
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* configure GPIO pads for audio. Mainboard is expected to perform all GPIO
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* configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
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* configuration for audio pads.
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*/
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m_cfg->PchHdaAudioLinkHdaEnable = 0;
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memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
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memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
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memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
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m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
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m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
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m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable;
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/* Disable all PCIe clock sources by default. And set RP irrelevant clock. */
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for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) {
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if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
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m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
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else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN)
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m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;
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else
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m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED;
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m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED;
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}
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/* PCIE ports */
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m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
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pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp,
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CONFIG_MAX_PCH_ROOT_PORTS);
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/* CPU PCIE ports */
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m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table());
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pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp,
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CONFIG_MAX_CPU_ROOT_PORTS);
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/* ISH */
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dev = pcidev_path_on_root(PCH_DEVFN_ISH);
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m_cfg->PchIshEnable = is_dev_enabled(dev);
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/* Tcss USB */
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dev = pcidev_path_on_root(SA_DEVFN_TCSS_XHCI);
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m_cfg->TcssXhciEn = is_dev_enabled(dev);
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dev = pcidev_path_on_root(SA_DEVFN_TCSS_XDCI);
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m_cfg->TcssXdciEn = is_dev_enabled(dev);
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/* TCSS DMA */
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dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0);
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m_cfg->TcssDma0En = is_dev_enabled(dev);
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dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1);
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m_cfg->TcssDma1En = is_dev_enabled(dev);
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/* USB4/TBT */
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dev = pcidev_path_on_root(SA_DEVFN_TBT0);
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m_cfg->TcssItbtPcie0En = is_dev_enabled(dev);
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dev = pcidev_path_on_root(SA_DEVFN_TBT1);
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m_cfg->TcssItbtPcie1En = is_dev_enabled(dev);
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dev = pcidev_path_on_root(SA_DEVFN_TBT2);
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m_cfg->TcssItbtPcie2En = is_dev_enabled(dev);
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dev = pcidev_path_on_root(SA_DEVFN_TBT3);
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m_cfg->TcssItbtPcie3En = is_dev_enabled(dev);
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/* Vt-D config */
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/* Disable VT-d support for pre-QS platform */
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m_cfg->VtdDisable = 1;
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/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
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m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
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/* Skip CPU replacement check */
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m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
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m_cfg->TmeEnable = CONFIG(INTEL_TME);
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/* Skip GPIO configuration from FSP */
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m_cfg->GpioOverride = 0x1;
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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const struct soc_intel_alderlake_config *config;
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FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
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config = config_of_soc();
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soc_memory_init_params(m_cfg, config);
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mainboard_memory_init_params(mupd);
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}
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__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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