326 lines
8.6 KiB
C
326 lines
8.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_CHIP_H_
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#define _SOC_CHIP_H_
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <intelblocks/cfg.h>
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#include <intelblocks/gpio.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/pcie_rp.h>
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#include <intelblocks/tcss.h>
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#include <soc/gpe.h>
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#include <soc/pci_devs.h>
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#include <soc/pmc.h>
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#include <soc/serialio.h>
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#include <soc/usb.h>
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#include <stdint.h>
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struct soc_intel_alderlake_config {
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/* Common struct containing soc config data required by common code */
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struct soc_intel_common_config common_soc_config;
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/* Common struct containing power limits configuration information */
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struct soc_power_limits_config power_limits_config;
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/* Gpio group routed to each dword of the GPE0 block. Values are
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* of the form PMC_GPP_[A:U] or GPD. */
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uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
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uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
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uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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/* Enable S0iX support */
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int s0ix_enable;
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/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
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uint8_t TcssD3HotDisable;
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/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
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uint8_t TcssD3ColdDisable;
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/* Enable DPTF support */
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int dptf_enable;
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/* Deep SX enable for both AC and DC */
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int deep_s3_enable_ac;
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int deep_s3_enable_dc;
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int deep_s5_enable_ac;
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int deep_s5_enable_dc;
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/* Deep Sx Configuration
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* DSX_EN_WAKE_PIN - Enable WAKE# pin
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* DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
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* DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
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uint32_t deep_sx_config;
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/* TCC activation offset */
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uint32_t tcc_offset;
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/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
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* When enabled memory will be training at two different frequencies.
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* 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
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* 4:FixedPoint3, 5:Enabled */
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enum {
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SaGv_Disabled,
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SaGv_FixedPoint0,
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SaGv_FixedPoint1,
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SaGv_FixedPoint2,
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SaGv_FixedPoint3,
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SaGv_Enabled,
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} SaGv;
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/* Rank Margin Tool. 1:Enable, 0:Disable */
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uint8_t RMT;
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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struct usb3_port_config usb3_ports[10];
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/* Wake Enable Bitmap for USB2 ports */
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uint16_t usb2_wake_enable_bitmap;
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/* Wake Enable Bitmap for USB3 ports */
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uint16_t usb3_wake_enable_bitmap;
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/* Program OC pins for TCSS */
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struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
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/* SATA related */
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uint8_t SataEnable;
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uint8_t SataMode;
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uint8_t SataSalpSupport;
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uint8_t SataPortsEnable[8];
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uint8_t SataPortsDevSlp[8];
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/*
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* Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
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* Default 0. Setting this to 1 disables the SATA Power Optimizer.
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*/
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uint8_t SataPwrOptimizeDisable;
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/*
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* SATA Port Enable Dito Config.
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* Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
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*/
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uint8_t SataPortsEnableDitoConfig[8];
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/* SataPortsDmVal is the DITO multiplier. Default is 15. */
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uint8_t SataPortsDmVal[8];
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/* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
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uint16_t SataPortsDitoVal[8];
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/* Audio related */
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uint8_t PchHdaDspEnable;
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/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
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enum {
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HDA_TMODE_2T = 0,
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HDA_TMODE_4T = 2,
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HDA_TMODE_8T = 3,
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HDA_TMODE_16T = 4,
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} PchHdaIDispLinkTmode;
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/* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */
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enum {
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HDA_LINKFREQ_48MHZ = 3,
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HDA_LINKFREQ_96MHZ = 4,
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} PchHdaIDispLinkFrequency;
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bool PchHdaIDispCodecEnable;
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struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS];
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struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS];
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uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC];
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/* Gfx related */
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enum {
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IGD_SM_0MB = 0x00,
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IGD_SM_32MB = 0x01,
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IGD_SM_64MB = 0x02,
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IGD_SM_96MB = 0x03,
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IGD_SM_128MB = 0x04,
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IGD_SM_160MB = 0x05,
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IGD_SM_4MB = 0xF0,
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IGD_SM_8MB = 0xF1,
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IGD_SM_12MB = 0xF2,
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IGD_SM_16MB = 0xF3,
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IGD_SM_20MB = 0xF4,
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IGD_SM_24MB = 0xF5,
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IGD_SM_28MB = 0xF6,
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IGD_SM_36MB = 0xF8,
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IGD_SM_40MB = 0xF9,
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IGD_SM_44MB = 0xFA,
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IGD_SM_48MB = 0xFB,
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IGD_SM_52MB = 0xFC,
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IGD_SM_56MB = 0xFD,
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IGD_SM_60MB = 0xFE,
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} IgdDvmt50PreAlloc;
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uint8_t SkipExtGfxScan;
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/* HeciEnabled decides the state of Heci1 at end of boot
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* Setting to 0 (default) disables Heci1 and hides the device from OS */
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uint8_t HeciEnabled;
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/* PL2 Override value in Watts */
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uint32_t tdp_pl2_override;
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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uint8_t eist_enable;
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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uint8_t PmTimerDisabled;
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/*
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* SerialIO device mode selection:
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* PchSerialIoDisabled,
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* PchSerialIoPci,
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* PchSerialIoHidden,
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* PchSerialIoLegacyUart,
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* PchSerialIoSkipInit
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*/
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uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
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uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
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uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
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/*
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* GSPIn Default Chip Select Mode:
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* 0:Hardware Mode,
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* 1:Software Mode
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*/
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uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
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/*
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* GSPIn Default Chip Select State:
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* 0: Low,
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* 1: High
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*/
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uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
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/* Debug interface selection */
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enum {
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DEBUG_INTERFACE_RAM = (1 << 0),
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DEBUG_INTERFACE_UART_8250IO = (1 << 1),
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DEBUG_INTERFACE_USB3 = (1 << 3),
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DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4),
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DEBUG_INTERFACE_TRACEHUB = (1 << 5),
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} debug_interface_flag;
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/* Enable Pch iSCLK */
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uint8_t pch_isclk;
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/* CNVi BT Core Enable/Disable */
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bool CnviBtCore;
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/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
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bool CnviBtAudioOffload;
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/*
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* IOM Port Config
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* If a port orientation needs to be controlled by the SOC this setting must be
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* updated to reflect the correct GPIOs being used for the SOC port flipping.
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* There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down
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* 0,1 are pull up and pull down for port 0
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* 2,3 are pull up and pull down for port 1
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* 4,5 are pull up and pull down for port 2
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* 6,7 are pull up and pull down for port 3
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* values to be programmed correspond to the GPIO family and offsets
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*/
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uint32_t IomTypeCPortPadCfg[8];
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/*
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* SOC Aux orientation override:
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* This is a bitfield that corresponds to up to 4 TCSS ports on ADL.
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* Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
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* Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
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* on the motherboard.
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*/
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uint16_t TcssAuxOri;
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/* Connect Topology Command timeout value */
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uint16_t ITbtConnectTopologyTimeoutInMs;
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/*
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* Override GPIO PM configuration:
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* 0: Use FSP default GPIO PM program,
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* 1: coreboot to override GPIO PM program
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*/
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uint8_t gpio_override_pm;
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/*
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* GPIO PM configuration: 0 to disable, 1 to enable power gating
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* Bit 6-7: Reserved
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* Bit 5: MISCCFG_GPSIDEDPCGEN
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* Bit 4: MISCCFG_GPRCOMPCDLCGEN
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* Bit 3: MISCCFG_GPRTCDLCGEN
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* Bit 2: MISCCFG_GSXLCGEN
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* Bit 1: MISCCFG_GPDPCGEN
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* Bit 0: MISCCFG_GPDLCGEN
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*/
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uint8_t gpio_pm[TOTAL_GPIO_COMM];
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/* DP config */
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/*
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* Port config
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* 0:Disabled, 1:eDP, 2:MIPI DSI
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*/
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uint8_t DdiPortAConfig;
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uint8_t DdiPortBConfig;
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/* Enable(1)/Disable(0) HPD */
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uint8_t DdiPortAHpd;
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uint8_t DdiPortBHpd;
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uint8_t DdiPortCHpd;
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uint8_t DdiPort1Hpd;
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uint8_t DdiPort2Hpd;
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uint8_t DdiPort3Hpd;
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uint8_t DdiPort4Hpd;
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/* Enable(1)/Disable(0) DDC */
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uint8_t DdiPortADdc;
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uint8_t DdiPortBDdc;
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uint8_t DdiPortCDdc;
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uint8_t DdiPort1Ddc;
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uint8_t DdiPort2Ddc;
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uint8_t DdiPort3Ddc;
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uint8_t DdiPort4Ddc;
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/* Hybrid storage mode enable (1) / disable (0)
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* This mode makes FSP detect Optane and NVME and set PCIe lane mode
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* accordingly */
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uint8_t HybridStorageMode;
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/*
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* Override CPU flex ratio value:
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* CPU ratio value controls the maximum processor non-turbo ratio.
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* Valid Range 0 to 63.
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*
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* In general descriptor provides option to set default cpu flex ratio.
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* Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
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* That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
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*
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* Only override CPU flex ratio if don't want to boot with non-turbo max.
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*/
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uint8_t cpu_ratio_override;
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/*
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* Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
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* Default 0. Setting this to 1 disables the DMI Power Optimizer.
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*/
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uint8_t DmiPwrOptimizeDisable;
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/*
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* Enable(1)/Disable(0) CPU Replacement check.
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* Default 0. Setting this to 1 to check CPU replacement.
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*/
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uint8_t CpuReplacementCheck;
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/* ISA Serial Base selection. */
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enum {
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ISA_SERIAL_BASE_ADDR_3F8,
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ISA_SERIAL_BASE_ADDR_2F8,
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} IsaSerialUartBase;
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};
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typedef struct soc_intel_alderlake_config config_t;
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#endif
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