349 lines
10 KiB
Plaintext
349 lines
10 KiB
Plaintext
chip soc/intel/alderlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_C"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# TCSS
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register "TcssAuxOri" = "1"
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register "IomTypeCPortPadCfg[0]" = "0x09020005"
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register "IomTypeCPortPadCfg[1]" = "0x09020006"
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# Enable heci communication
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register "HeciEnabled" = "1"
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# Enable CNVi Bluetooth
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register "CnviBtCore" = "true"
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# FSP configuration
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register "SaGv" = "SaGv_Disabled"
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# S0ix enable
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register "s0ix_enable" = "1"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port A0
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register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Type-A Port A1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-A / Type-C Cl
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
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register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A / Type-C Co
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# Enable PCH PCIE RP 5 using CLK 1
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable NVMe PCIE 9 using clk 0
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 0,
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.clk_req = 0,
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.flags = PCIE_RP_LTR,
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}"
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# Enable SD Card PCIE 8 using clk 3
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register "pch_pcie_rp[PCH_RP(8)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
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}"
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# Enable SATA
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register "SataEnable" = "1"
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register "SataMode" = "0"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable[0]" = "0"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[1]" = "1"
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register "SataPortsEnableDitoConfig[1]" = "1"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoPci,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 1,
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}"
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register "SerialIoGSpiCsState" = "{
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[PchSerialIoIndexGSPI0] = 1,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoPci,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
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register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
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register "PchHdaIDispCodecEnable" = "1"
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# DP port
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register "DdiPortAConfig" = "1" # eDP
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register "DdiPortBConfig" = "0"
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register "DdiPortAHpd" = "1"
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register "DdiPortBHpd" = "1"
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register "DdiPortCHpd" = "0"
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register "DdiPort1Hpd" = "1"
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register "DdiPort2Hpd" = "1"
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register "DdiPort3Hpd" = "0"
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register "DdiPort4Hpd" = "0"
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register "DdiPortADdc" = "0"
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register "DdiPortBDdc" = "1"
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register "DdiPortCDdc" = "0"
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register "DdiPort1Ddc" = "0"
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register "DdiPort2Ddc" = "0"
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register "DdiPort3Ddc" = "0"
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register "DdiPort4Ddc" = "0"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| GSPI1 | Fingerprint MCU |
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#| I2C0 | SAR0, WWAN, HDMI |
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#| I2C1 | Camera |
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#| I2C2 | Audio |
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#| I2C3 | Touchscreen, USI |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Graphics
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device pci 04.0 on end # DPTF
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device pci 05.0 on end # IPU
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device pci 06.0 off end # PEG60
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device pci 07.0 on end # TBT_PCIe0
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device pci 07.1 on end # TBT_PCIe1
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device pci 07.2 on end # TBT_PCIe2
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device pci 07.3 on end # TBT_PCIe3
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device pci 08.0 off end # GNA
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device pci 09.0 off end # NPK
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device pci 0a.0 off end # Crash-log SRAM
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device pci 0d.0 on end # USB xHCI
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device pci 0d.1 off end # USB xDCI (OTG)
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device pci 0d.2 on
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chip drivers/intel/usb4/retimer
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register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19)"
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device generic 0 on end
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end
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end
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device pci 0d.3 on end # TBT DMA1
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device pci 0e.0 off end # VMD
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device pci 10.0 off end
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device pci 10.1 off end
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device pci 10.6 off end # THC0
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device pci 10.7 off end # THC1
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device pci 11.0 off end
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device pci 11.1 off end
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device pci 11.2 off end
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device pci 11.3 off end
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device pci 11.4 off end
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device pci 11.5 off end
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device pci 12.0 off end # SensorHUB
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device pci 12.5 off end
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device pci 12.6 off end # GSPI2
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device pci 13.0 off end # GSPI3
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device pci 13.1 off end
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device pci 14.0 on
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chip drivers/usb/acpi
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register "desc" = ""Root Hub""
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register "type" = "UPC_TYPE_HUB"
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device usb 0.0 on
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chip drivers/usb/acpi
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register "desc" = ""Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
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device usb 2.9 on end
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end
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end
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end
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end # USB3.1 xHCI
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device pci 14.1 off end # USB3.1 xDCI
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device pci 14.2 off end # Shared RAM
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device pci 14.3 on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end # CNVi: WiFi
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device pci 15.0 on end # I2C0
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device pci 15.1 on end # I2C1
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device pci 15.2 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F9)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "0"
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register "imon_slot_no" = "1"
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register "uid" = "0"
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register "desc" = ""Right Speaker Amp""
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register "name" = ""MAXR""
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device i2c 31 on end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "2"
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register "imon_slot_no" = "3"
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register "uid" = "1"
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register "desc" = ""Left Speaker Amp""
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register "name" = ""MAXL""
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device i2c 32 on end
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end
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end # I2C2
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device pci 15.3 on end # I2C3
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device pci 16.0 off end # HECI1
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device pci 16.1 off end # HECI2
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device pci 16.2 off end # CSME
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device pci 16.3 off end # CSME
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device pci 16.4 off end # HECI3
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device pci 16.5 off end # HECI4
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device pci 17.0 on end # SATA
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device pci 19.0 off end # I2C4
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device pci 19.1 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
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register "wake" = "GPE0_DW2_15"
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register "probed" = "1"
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device i2c 15 on end
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end
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end # I2C5
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device pci 19.2 off end # UART2
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device pci 1c.0 off end # RP1
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device pci 1c.1 off end # RP2
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device pci 1c.2 off end # RP3
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device pci 1c.3 off end # RP4
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device pci 1c.4 on end # RP5
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device pci 1c.5 off end # RP6
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device pci 1c.6 off end # RP7
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device pci 1c.7 on end # RP8
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device pci 1d.0 on end # RP9
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device pci 1d.1 off end # RP10
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device pci 1d.2 off end # RP11
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device pci 1d.3 off end # RP12
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device pci 1e.0 on end # UART0
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device pci 1e.1 off end # UART1
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device pci 1e.2 on
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chip drivers/spi/acpi
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "compat_string" = ""google,cr50""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C3_IRQ)"
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device spi 0 on end
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end
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end # GSPI0
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device pci 1e.3 off end # GSPI1
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device pci 1f.0 on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end # eSPI
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device pci 1f.1 on end # P2SB
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device pci 1f.2 hidden
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# The pmc_mux chip driver is a placeholder for the
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# PMC.MUX device in the ACPI hierarchy.
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "6"
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register "usb3_port_number" = "1"
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# SBU is fixed, HSL follows CC
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register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "4"
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register "usb3_port_number" = "2"
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# SBU is fixed, HSL follows CC
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register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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device generic 1 alias conn1 on end
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end
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end
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end
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end # PMC
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device pci 1f.3 on end # Intel Audio SNDW
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # SPI
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device pci 1f.6 off end # GbE
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end
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end
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