151 lines
3.5 KiB
C
151 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <assert.h>
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#include <intelblocks/acpi.h>
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#include <soc/pci_devs.h>
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#include <soc/util.h>
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#include "chip.h"
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/*
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* List of supported C-states in this processor.
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*/
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enum {
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C_STATE_C1, /* 0 */
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C_STATE_C3, /* 1 */
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C_STATE_C6, /* 2 */
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C_STATE_C7, /* 3 */
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NUM_C_STATES
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};
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static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
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[C_STATE_C1] = {
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/* C1 */
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.latency = 1,
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.power = 0x3e8,
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.resource = MWAIT_RES(0, 0),
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},
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[C_STATE_C3] = {
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/* C3 */
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.latency = 15,
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.power = 0x1f4,
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.resource = MWAIT_RES(1, 0),
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},
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[C_STATE_C6] = {
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/* C6 */
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.latency = 41,
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.power = 0x15e,
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.resource = MWAIT_RES(2, 0),
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},
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[C_STATE_C7] = {
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/* C7 */
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.latency = 41,
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.power = 0x0c8,
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.resource = MWAIT_RES(3, 0),
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}
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};
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/* Max states supported */
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static int cstate_set_all[] = {
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C_STATE_C1,
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C_STATE_C3,
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C_STATE_C6,
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C_STATE_C7
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};
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static int cstate_set_c1_c6[] = {
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C_STATE_C1,
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C_STATE_C6,
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};
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acpi_cstate_t *soc_get_cstate_map(size_t *entries)
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{
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static acpi_cstate_t map[ARRAY_SIZE(cstate_set_all)];
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int *cstate_set;
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int i;
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const config_t *config = config_of_soc();
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const enum acpi_cstate_mode states = config->cstate_states;
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switch (states) {
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case CSTATES_C1C6:
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*entries = ARRAY_SIZE(cstate_set_c1_c6);
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cstate_set = cstate_set_c1_c6;
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break;
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case CSTATES_ALL:
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default:
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*entries = ARRAY_SIZE(cstate_set_all);
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cstate_set = cstate_set_all;
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break;
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}
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for (i = 0; i < *entries; i++) {
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map[i] = cstate_map[cstate_set[i]];
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map[i].ctype = i + 1;
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}
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return map;
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}
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static void print_madt_ioapic(int socket, int stack,
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int ioapic_id, uint32_t ioapic_base, int gsi_base)
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{
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printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, "
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"ioapic_base: 0x%x, gsi_base: 0x%x\n",
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socket, stack, ioapic_id, ioapic_base, gsi_base);
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return;
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}
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const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries)
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{
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int cur_index;
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const IIO_UDS *hob = get_iio_uds();
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/* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */
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#if (CONFIG(SOC_INTEL_COOPERLAKE_SP))
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const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 };
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#endif
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#if (CONFIG(SOC_INTEL_SKYLAKE_SP))
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const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 };
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#endif
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static struct madt_ioapic_info madt_tbl[ARRAY_SIZE(gsi_bases)];
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cur_index = 0;
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madt_tbl[cur_index].id = PCH_IOAPIC_ID;
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madt_tbl[cur_index].addr = hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase;
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madt_tbl[cur_index].gsi_base = gsi_bases[cur_index];
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print_madt_ioapic(0, 0, madt_tbl[cur_index].id,
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madt_tbl[cur_index].addr, madt_tbl[cur_index].gsi_base);
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++cur_index;
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for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
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for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
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const STACK_RES *ri =
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&hob->PlatformData.IIO_resource[socket].StackRes[stack];
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if (!is_iio_stack_res(ri))
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continue;
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assert(cur_index < ARRAY_SIZE(gsi_bases));
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madt_tbl[cur_index].id = soc_get_iio_ioapicid(socket, stack);
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madt_tbl[cur_index].gsi_base = gsi_bases[cur_index];
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madt_tbl[cur_index].addr = ri->IoApicBase;
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/*
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* Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
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* The IIO IOAPIC is placed at 0x1000 from the reported base.
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*/
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if (stack == 0 && socket == 0)
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madt_tbl[cur_index].addr += 0x1000;
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print_madt_ioapic(socket, stack, madt_tbl[cur_index].id,
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madt_tbl[cur_index].addr,
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madt_tbl[cur_index].gsi_base);
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++cur_index;
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}
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}
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*entries = cur_index;
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return madt_tbl;
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}
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