192 lines
5.2 KiB
C
192 lines
5.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <delay.h>
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#include <stdint.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <device/pci_def.h>
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <pc80/mc146818rtc.h>
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#include <console/console.h>
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#include <cpu/x86/bist.h>
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#include <cpu/intel/speedstep.h>
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#include "southbridge/intel/i3100/early_smbus.c"
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#include "southbridge/intel/i3100/early_lpc.c"
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#include "reset.c"
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#include "superio/intel/i3100/early_serial.c"
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#include "superio/smsc/smscsuperio/early_serial.c"
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#include "northbridge/intel/i3100/i3100.h"
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#include "southbridge/intel/i3100/i3100.h"
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#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
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#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
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#define RCBA_RPC 0x0224 /* 32 bit */
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#define RCBA_TCTL 0x3000 /* 8 bit */
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#define RCBA_D31IP 0x3100 /* 32 bit */
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#define RCBA_D30IP 0x3104 /* 32 bit */
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#define RCBA_D29IP 0x3108 /* 32 bit */
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#define RCBA_D28IP 0x310C /* 32 bit */
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#define RCBA_D31IR 0x3140 /* 16 bit */
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#define RCBA_D30IR 0x3142 /* 16 bit */
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#define RCBA_D29IR 0x3144 /* 16 bit */
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#define RCBA_D28IR 0x3146 /* 16 bit */
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#define RCBA_RTC 0x3400 /* 32 bit */
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#define RCBA_HPTC 0x3404 /* 32 bit */
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#define RCBA_GCS 0x3410 /* 32 bit */
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#define RCBA_BUC 0x3414 /* 8 bit */
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#define RCBA_FD 0x3418 /* 32 bit */
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#define RCBA_PRC 0x341C /* 32 bit */
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static inline int spd_read_byte(u16 device, u8 address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/intel/i3100/raminit.h"
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#include "northbridge/intel/i3100/memory_initialized.c"
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#include "northbridge/intel/i3100/raminit.c"
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#include "lib/generic_sdram.c"
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#include "northbridge/intel/i3100/reset_test.c"
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#include "debug.c"
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#include <spd.h>
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#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
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static void early_config(void)
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{
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u32 gcs, rpc, fd;
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/* Enable RCBA */
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pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
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/* Disable watchdog */
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gcs = read32(DEFAULT_RCBA + RCBA_GCS);
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gcs |= (1 << 5); /* No reset */
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write32(DEFAULT_RCBA + RCBA_GCS, gcs);
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/* Configure PCIe port B as 4x */
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rpc = read32(DEFAULT_RCBA + RCBA_RPC);
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rpc |= (3 << 0);
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write32(DEFAULT_RCBA + RCBA_RPC, rpc);
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/* Disable Modem, Audio, PCIe ports 2/3/4 */
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fd = read32(DEFAULT_RCBA + RCBA_FD);
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fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
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write32(DEFAULT_RCBA + RCBA_FD, fd);
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/* Enable HPET */
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write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
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/* Improve interrupt routing
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* D31:F2 SATA INTB# -> PIRQD
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* D31:F3 SMBUS INTB# -> PIRQD
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* D31:F4 CHAP INTD# -> PIRQA
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* D29:F0 USB1#1 INTA# -> PIRQH
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* D29:F1 USB1#2 INTB# -> PIRQD
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* D29:F7 USB2 INTA# -> PIRQH
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* D28:F0 PCIe Port 1 INTA# -> PIRQE
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*/
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write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);
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write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);
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write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);
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write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);
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/* Setup sata mode */
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pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
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}
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void main(unsigned long bist)
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{
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/* int boot_mode = 0; */
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static const struct mem_controller mch[] = {
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x00, 0),
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.f1 = PCI_DEV(0, 0x00, 1),
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.f2 = PCI_DEV(0, 0x00, 2),
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.f3 = PCI_DEV(0, 0x00, 3),
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.channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
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.channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
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}
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};
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if (bist == 0)
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enable_lapic();
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/* Setup the console */
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i3100_enable_superio();
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i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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/* Perform early board specific init */
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early_config();
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/* Prevent the TCO timer from rebooting us */
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i3100_halt_tco_timer();
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/* Enable SPD ROMs and DDR-II DRAM */
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enable_smbus();
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/* Enable SpeedStep and automatic thermal throttling */
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{
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msr_t msr;
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u16 perf;
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msr = rdmsr(IA32_MISC_ENABLES);
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msr.lo |= (1 << 3) | (1 << 16);
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wrmsr(IA32_MISC_ENABLES, msr);
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/* Set CPU frequency/voltage to maximum */
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/* Read performance status register and keep
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* bits 47:32, where BUS_RATIO_MAX and VID_MAX
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* are encoded
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*/
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msr = rdmsr(IA32_PERF_STS);
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perf = msr.hi & 0x0000ffff;
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/* Write VID_MAX & BUS_RATIO_MAX to
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* performance control register
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*/
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msr = rdmsr(IA32_PERF_CTL);
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msr.lo &= 0xffff0000;
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msr.lo |= perf;
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wrmsr(IA32_PERF_CTL, msr);
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}
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/* Initialize memory */
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sdram_initialize(ARRAY_SIZE(mch), mch);
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}
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