42 lines
1.3 KiB
C
42 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/* Magic value used to locate speedstep configuration in the device tree */
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#define SPEEDSTEP_APIC_MAGIC 0xACAC
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/* MWAIT coordination I/O base address. This must match
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* the \_PR_.CPU0 PM base address.
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*/
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#define PMB0_BASE 0x510
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/* PMB1: I/O port that triggers SMI once cores are in the same state.
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* See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
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*/
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#define PMB1_BASE 0x800
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/* Speedstep related MSRs */
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#define IA32_PLATFORM_ID 0x017
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#define IA32_PERF_STS 0x198
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#define IA32_PERF_CTL 0x199
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#define MSR_THERM2_CTL 0x19D
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#define IA32_MISC_ENABLES 0x1A0
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