271 lines
6.6 KiB
C
271 lines
6.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/intel/microcode.h>
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#include <cpu/intel/speedstep.h>
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#include <cpu/intel/hyperthreading.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/name.h>
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#include <usbdebug.h>
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static const uint32_t microcode_updates[] = {
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#include "microcode-2129-m206f257.h"
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#include "microcode-2334-m016fbB6.h"
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#include "microcode-2336-m106fbB6.h"
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#include "microcode-2337-m806fbB6.h"
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#include "microcode-2346-m16fda3.h"
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#include "microcode-2347-m206fda3.h"
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#include "microcode-2348-m806fda3.h"
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#include "microcode-2374-m16f6cb.h"
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#include "microcode-2375-m206f6cc.h"
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#include "microcode-2376-m46f6cd.h"
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#include "microcode-2380-m106f768.h"
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#include "microcode-2381-m406f769.h"
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#include "microcode-2385-m806fa94.h"
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#include "microcode-2389-m16f25a.h"
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#include "microcode-2986-m086fbB8.h"
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#include "microcode-2990-m046fbB9.h"
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#include "microcode-2991-m406fbB9.h"
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/* Dummy terminator */
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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};
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#define IA32_FEATURE_CONTROL 0x003a
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#define CPUID_VMX (1 << 5)
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#define CPUID_SMX (1 << 6)
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static void enable_vmx(void)
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{
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struct cpuid_result regs;
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msr_t msr;
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msr = rdmsr(IA32_FEATURE_CONTROL);
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if (msr.lo & (1 << 0)) {
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/* VMX locked. If we set it again we get an illegal
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* instruction
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*/
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return;
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}
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regs = cpuid(1);
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if (regs.ecx & CPUID_VMX) {
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msr.lo |= (1 << 2);
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if (regs.ecx & CPUID_SMX)
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msr.lo |= (1 << 1);
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}
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wrmsr(IA32_FEATURE_CONTROL, msr);
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msr.lo |= (1 << 0); /* Set lock bit */
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wrmsr(IA32_FEATURE_CONTROL, msr);
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}
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#define PMG_CST_CONFIG_CONTROL 0xe2
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#define PMG_IO_BASE_ADDR 0xe3
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#define PMG_IO_CAPTURE_ADDR 0xe4
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#define HIGHEST_CLEVEL 3
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static void configure_c_states(void)
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{
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msr_t msr;
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msr = rdmsr(PMG_CST_CONFIG_CONTROL);
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msr.lo |= (1 << 15); // config lock until next reset
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msr.lo |= (1 << 14); // Deeper Sleep
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msr.lo |= (1 << 10); // Enable IO MWAIT redirection
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msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
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msr.lo |= (1 << 3); // Dynamic L2
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/* Number of supported C-States */
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msr.lo &= ~7;
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msr.lo |= HIGHEST_CLEVEL; // support at most C3
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wrmsr(PMG_CST_CONFIG_CONTROL, msr);
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/* Set Processor MWAIT IO BASE */
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msr.hi = 0;
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msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
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wrmsr(PMG_IO_BASE_ADDR, msr);
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/* Set C_LVL controls and IO Capture Address */
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msr.hi = 0;
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msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
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wrmsr(PMG_IO_CAPTURE_ADDR, msr);
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}
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#define IA32_MISC_ENABLE 0x1a0
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#define IA32_PECI_CTL 0x5a0
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static void configure_misc(void)
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{
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msr_t msr;
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 3); /* TM1 enable */
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msr.lo |= (1 << 13); /* TM2 enable */
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msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */
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msr.lo |= (1 << 10); /* FERR# multiplexing */
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// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
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msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
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/* Enable C2E */
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msr.lo |= (1 << 26);
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/* Enable C4E */
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/* TODO This should only be done on mobile CPUs, see cpuid 5 */
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msr.hi |= (1 << (32 - 32)); // C4E
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msr.hi |= (1 << (33 - 32)); // Hard C4E
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/* Enable EMTTM. */
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/* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */
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msr.hi |= (1 << (36 - 32));
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wrmsr(IA32_MISC_ENABLE, msr);
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msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
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wrmsr(IA32_MISC_ENABLE, msr);
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// set maximum CPU speed
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msr = rdmsr(IA32_PERF_STS);
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int busratio_max=(msr.hi >> (40-32)) & 0x1f;
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msr = rdmsr(IA32_PLATFORM_ID);
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int vid_max=msr.lo & 0x3f;
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msr.lo &= ~0xffff;
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msr.lo |= busratio_max << 8;
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msr.lo |= vid_max;
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wrmsr(IA32_PERF_CTL, msr);
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/* Enable PECI */
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msr = rdmsr(IA32_PECI_CTL);
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msr.lo |= 1;
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wrmsr(IA32_PECI_CTL, msr);
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}
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#define PIC_SENS_CFG 0x1aa
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static void configure_pic_thermal_sensors(void)
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{
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msr_t msr;
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msr = rdmsr(PIC_SENS_CFG);
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msr.lo |= (1 << 21); // inter-core lock TM1
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msr.lo |= (1 << 4); // Enable bypass filter
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wrmsr(PIC_SENS_CFG, msr);
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}
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#if CONFIG_USBDEBUG
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static unsigned ehci_debug_addr;
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#endif
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static void model_6fx_init(device_t cpu)
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{
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char processor_name[49];
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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/* Update the microcode */
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intel_update_microcode(microcode_updates);
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/* Print processor name */
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fill_processor_name(processor_name);
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printk(BIOS_INFO, "CPU: %s.\n", processor_name);
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#if CONFIG_USBDEBUG
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// Is this caution really needed?
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if(!ehci_debug_addr)
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ehci_debug_addr = get_ehci_debug();
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set_ehci_debug(0);
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#endif
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/* Setup MTRRs */
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x86_setup_mtrrs();
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x86_mtrr_check();
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/* Setup Page Attribute Tables (PAT) */
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// TODO set up PAT
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#if CONFIG_USBDEBUG
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set_ehci_debug(ehci_debug_addr);
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#endif
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/* Enable the local cpu apics */
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setup_lapic();
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/* Enable virtualization */
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enable_vmx();
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/* Configure C States */
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configure_c_states();
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/* Configure Enhanced SpeedStep and Thermal Sensors */
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configure_misc();
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/* PIC thermal sensor control */
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configure_pic_thermal_sensors();
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/* Start up my cpu siblings */
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intel_sibling_init(cpu);
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_6fx_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_INTEL, 0x06f0 }, /* Intel Core 2 Solo/Core Duo */
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{ X86_VENDOR_INTEL, 0x06f2 }, /* Intel Core 2 Solo/Core Duo */
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{ X86_VENDOR_INTEL, 0x06f6 }, /* Intel Core 2 Solo/Core Duo */
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{ X86_VENDOR_INTEL, 0x06f7 }, /* Intel Core 2 Solo/Core Duo */
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{ X86_VENDOR_INTEL, 0x06fa }, /* Intel Core 2 Solo/Core Duo */
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{ X86_VENDOR_INTEL, 0x06fb }, /* Intel Core 2 Solo/Core Duo */
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{ X86_VENDOR_INTEL, 0x06fd }, /* Intel Core 2 Solo/Core Duo */
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{ X86_VENDOR_INTEL, 0x10676 }, /* Core2 Duo E8200 */
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{ 0, 0 },
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};
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static const struct cpu_driver driver __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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