301 lines
9.0 KiB
C
301 lines
9.0 KiB
C
/*
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*
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* Copyright (C) 2012 secunet Security Networks AG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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//#define DEBUG_STATUS
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <libpayload.h>
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#include <pci.h>
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#include <pci/pci.h>
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#include <storage/ata.h>
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#include <storage/ahci.h>
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#include "ahci_private.h"
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#ifdef DEBUG_STATUS
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static inline u32 _ahci_clear_status(volatile u32 *const reg,
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const char *const r,
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const char *const f)
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{
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const u32 bits = *reg;
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if (bits)
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*reg = bits;
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printf("ahci: %s: %s == 0x%08x\n", f, r, bits);
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return bits;
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}
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#define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r, #r, __func__)
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#else
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static inline u32 _ahci_clear_status(volatile u32 *const reg)
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{
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const u32 bits = *reg;
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if (bits)
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*reg = bits;
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return bits;
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}
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#define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r)
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#endif
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static inline int ahci_port_is_active(const hba_port_t *const port)
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{
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return (port->sata_status & (HBA_PxSSTS_IPM_MASK | HBA_PxSSTS_DET_MASK))
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== (HBA_PxSSTS_IPM_ACTIVE | HBA_PxSSTS_DET_ESTABLISHED);
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}
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/** Do minimal error recovery. */
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int ahci_error_recovery(ahci_dev_t *const dev, const u32 intr_status)
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{
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/* Command engine has to be restarted.
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We don't call ahci_cmdengine_stop() here as it also checks
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HBA_PxCMD_FR which won't clear on fatal errors. */
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dev->port->cmd_stat &= ~HBA_PxCMD_ST;
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/* Always clear sata_error. */
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ahci_clear_status(dev->port, sata_error);
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/* Perform COMRESET if appropriate. */
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const u32 tfd = dev->port->taskfile_data;
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if ((tfd & (HBA_PxTFD_BSY | HBA_PxTFD_DRQ)) |
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(intr_status & HBA_PxIS_PCS)) {
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const u32 sctl = dev->port->sata_control & ~HBA_PxSCTL_DET_MASK;
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dev->port->sata_control = sctl | HBA_PxSCTL_DET_COMRESET;
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mdelay(1);
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dev->port->sata_control = sctl;
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}
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if (ahci_port_is_active(dev->port))
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/* Start command engine. */
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return ahci_cmdengine_start(dev->port);
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else
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return -1;
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}
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static int ahci_dev_init(hba_ctrl_t *const ctrl,
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hba_port_t *const port,
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const int portnum)
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{
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int ret = 1;
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const int ncs = HBA_CAPS_DECODE_NCS(ctrl->caps);
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if (ahci_cmdengine_stop(port))
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return 1;
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/* Allocate command list, one command table and received FIS. */
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cmd_t *const cmdlist = memalign(1024, ncs * sizeof(cmd_t));
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cmdtable_t *const cmdtable = memalign(128, sizeof(cmdtable_t));
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rcvd_fis_t *const rcvd_fis = memalign(256, sizeof(rcvd_fis_t));
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/* Allocate our device structure. */
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ahci_dev_t *const dev = calloc(1, sizeof(ahci_dev_t));
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if (!cmdlist || !cmdtable || !rcvd_fis || !dev)
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goto _cleanup_ret;
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memset((void *)cmdlist, '\0', ncs * sizeof(cmd_t));
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memset((void *)cmdtable, '\0', sizeof(*cmdtable));
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memset((void *)rcvd_fis, '\0', sizeof(*rcvd_fis));
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/* Set command list base and received FIS base. */
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port->cmdlist_base = virt_to_phys(cmdlist);
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port->frameinfo_base = virt_to_phys(rcvd_fis);
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if (ahci_cmdengine_start(port))
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goto _cleanup_ret;
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/* Put port into active state. */
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port->cmd_stat |= HBA_PxCMD_ICC_ACTIVE;
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dev->ctrl = ctrl;
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dev->port = port;
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dev->cmdlist = cmdlist;
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dev->cmdtable = cmdtable;
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dev->rcvd_fis = rcvd_fis;
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/*
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* Wait for D2H Register FIS with device' signature.
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* The drive has to spin up here, so wait up to 30s.
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*/
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const int timeout_s = 30; /* Time out after 30s. */
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int timeout = timeout_s * 100;
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while ((port->taskfile_data & HBA_PxTFD_BSY) && timeout--)
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mdelay(10);
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if (port->taskfile_data & HBA_PxTFD_BSY)
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printf("ahci: Timed out after %d seconds "
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"of waiting for device to spin up.\n", timeout_s);
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/* Initialize device or fall through to clean up. */
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switch (port->signature) {
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case HBA_PxSIG_ATA:
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printf("ahci: ATA drive on port #%d.\n", portnum);
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#if CONFIG(LP_STORAGE_ATA)
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dev->ata_dev.identify = ahci_identify_device;
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dev->ata_dev.read_sectors = ahci_ata_read_sectors;
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return ata_attach_device(&dev->ata_dev, PORT_TYPE_SATA);
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#endif
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break;
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case HBA_PxSIG_ATAPI:
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printf("ahci: ATAPI drive on port #%d.\n", portnum);
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#if CONFIG(LP_STORAGE_ATAPI)
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dev->atapi_dev.identify = ahci_identify_device;
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dev->atapi_dev.packet_read_cmd = ahci_packet_read_cmd;
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return atapi_attach_device(&dev->atapi_dev, PORT_TYPE_SATA);
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#endif
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break;
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default:
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printf("ahci: Unsupported device (signature == 0x%08x) "
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"on port #%d.\n", port->signature, portnum);
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break;
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}
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ret = 2;
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_cleanup_ret:
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/* Clean up (not reached for initialized devices). */
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if (dev)
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free(dev);
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/* Only free if stopping succeeds, since otherwise the controller may
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still use the resources for DMA. */
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if (!ahci_cmdengine_stop(port)) {
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port->cmdlist_base = 0;
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port->frameinfo_base = 0;
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if (rcvd_fis)
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free((void *)rcvd_fis);
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if (cmdtable)
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free((void *)cmdtable);
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if (cmdlist)
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free((void *)cmdlist);
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}
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return ret;
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}
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static void ahci_port_probe(hba_ctrl_t *const ctrl,
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hba_port_t *const port,
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const int portnum)
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{
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/* If staggered spin-up is supported, spin-up device. */
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if (ctrl->caps & HBA_CAPS_SSS) {
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port->cmd_stat |= HBA_PxCMD_SUD;
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}
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/* Wait 1s if we just told the device to spin up or
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if it's the first port. */
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if ((ctrl->caps & HBA_CAPS_SSS) ||
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!(ctrl->ports_impl & ((1 << (portnum - 1)) - 1))) {
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/* Wait for port to become active. */
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int timeout = 100; /* Time out after 100 * 100us == 10ms. */
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while (!ahci_port_is_active(port) && timeout--)
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udelay(100);
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}
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if (!ahci_port_is_active(port))
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return;
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ahci_clear_status(port, sata_error);
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ahci_clear_status(port, intr_status);
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ahci_dev_init(ctrl, port, portnum);
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}
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#if CONFIG(LP_STORAGE_AHCI_ONLY_TESTED)
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static u32 working_controllers[] = {
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0x8086 | 0x2929 << 16, /* Mobile ICH9 */
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0x8086 | 0x1c03 << 16, /* Mobile Cougar Point PCH */
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0x8086 | 0x1e03 << 16, /* Mobile Panther Point PCH */
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0x8086 | 0xa102 << 16, /* Desktop / Mobile-Wks Sunrise Point PCH */
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0x8086 | 0x5ae3 << 16, /* Apollo Lake */
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};
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#endif
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static void ahci_init_pci(pcidev_t dev)
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{
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int i;
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const u16 class = pci_read_config16(dev, 0xa);
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if (class != 0x0106)
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return;
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const u16 vendor = pci_read_config16(dev, 0x00);
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const u16 device = pci_read_config16(dev, 0x02);
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#if CONFIG(LP_STORAGE_AHCI_ONLY_TESTED)
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const u32 vendor_device = pci_read_config32(dev, 0x0);
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for (i = 0; i < ARRAY_SIZE(working_controllers); ++i)
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if (vendor_device == working_controllers[i])
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break;
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if (i == ARRAY_SIZE(working_controllers)) {
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printf("ahci: Not using untested SATA controller "
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"%02x:%02x.%02x (%04x:%04x).\n", PCI_BUS(dev),
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PCI_SLOT(dev), PCI_FUNC(dev), vendor, device);
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return;
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}
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#endif
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printf("ahci: Found SATA controller %02x:%02x.%02x (%04x:%04x).\n",
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PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev), vendor, device);
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hba_ctrl_t *const ctrl = phys_to_virt(
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pci_read_config32(dev, 0x24) & ~0x3ff);
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hba_port_t *const ports = ctrl->ports;
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/* Reset host controller. */
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ctrl->global_ctrl |= HBA_CTRL_RESET;
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/* Reset has to be finished after 1s. */
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int timeout = 10 * 1000; /* Time out after 10,000 * 100us == 1s. */
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while (ctrl->global_ctrl & HBA_CTRL_RESET && timeout--)
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udelay(100);
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if (ctrl->global_ctrl & HBA_CTRL_RESET) {
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printf("ahci: ERROR: "
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"Controller reset didn't finish within 1s.\n");
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return;
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}
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/* Set AHCI access mode. */
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ctrl->global_ctrl |= HBA_CTRL_AHCI_EN;
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/* Enable bus mastering. */
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const u16 command = pci_read_config16(dev, PCI_COMMAND);
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pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER);
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/* Probe for devices. */
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for (i = 0; i < 32; ++i) {
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if (ctrl->ports_impl & (1 << i))
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ahci_port_probe(ctrl, &ports[i], i + 1);
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}
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}
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void ahci_initialize(void)
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{
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int bus, dev, func;
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for (bus = 0; bus < 256; ++bus) {
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for (dev = 0; dev < 32; ++dev) {
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const u16 class =
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pci_read_config16(PCI_DEV(bus, dev, 0), 0xa);
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if (class != 0xffff) {
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for (func = 0; func < 8; ++func)
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ahci_init_pci(PCI_DEV(bus, dev, func));
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}
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}
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}
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}
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