341 lines
8.7 KiB
C
341 lines
8.7 KiB
C
/*
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* Copyright (c) 2020 Qualcomm Technologies.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* For simplicity sake let's rely on coreboot initializing the UART. */
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#include <config.h>
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#include <libpayload.h>
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#include <sys/types.h>
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#define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK 0x1
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#define RX_FIFO_WC_MSK 0x1FFFFFF
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#define START_UART_TX 0x8000000
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union proto_word_len {
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u32 uart_tx_word_len;
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u32 spi_word_len;
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};
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union proto_tx_trans_len {
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u32 uart_tx_stop_bit_len;
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u32 i2c_tx_trans_len;
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u32 spi_tx_trans_len;
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};
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union proto_rx_trans_len {
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u32 uart_tx_trans_len;
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u32 i2c_rx_trans_len;
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u32 spi_rx_trans_len;
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};
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struct qup_regs {
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u32 geni_init_cfg_revision;
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u32 geni_s_init_cfg_revision;
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u8 _reserved1[0x10 - 0x08];
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u32 geni_general_cfg;
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u32 geni_rx_fifo_ctrl;
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u8 _reserved2[0x20 - 0x18];
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u32 geni_force_default_reg;
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u32 geni_output_ctrl;
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u32 geni_cgc_ctrl;
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u32 geni_char_cfg;
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u32 geni_char_data_n;
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u8 _reserved3[0x40 - 0x34];
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u32 geni_status;
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u32 geni_test_bus_ctrl;
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u32 geni_ser_m_clk_cfg;
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u32 geni_ser_s_clk_cfg;
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u32 geni_prog_rom_ctrl_reg;
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u8 _reserved4[0x60 - 0x54];
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u32 geni_clk_ctrl_ro;
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u32 fifo_if_disable_ro;
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u32 geni_fw_revision_ro;
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u32 geni_s_fw_revision_ro;
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u32 geni_fw_multilock_protns_ro;
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u32 geni_fw_multilock_msa_ro;
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u32 geni_fw_multilock_sp_ro;
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u32 geni_clk_sel;
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u32 geni_dfs_if_cfg;
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u8 _reserved5[0x100 - 0x084];
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u32 geni_cfg_reg0;
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u32 geni_cfg_reg1;
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u32 geni_cfg_reg2;
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u32 geni_cfg_reg3;
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u32 geni_cfg_reg4;
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u32 geni_cfg_reg5;
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u32 geni_cfg_reg6;
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u32 geni_cfg_reg7;
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u32 geni_cfg_reg8;
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u32 geni_cfg_reg9;
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u32 geni_cfg_reg10;
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u32 geni_cfg_reg11;
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u32 geni_cfg_reg12;
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u32 geni_cfg_reg13;
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u32 geni_cfg_reg14;
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u32 geni_cfg_reg15;
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u32 geni_cfg_reg16;
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u32 geni_cfg_reg17;
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u32 geni_cfg_reg18;
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u8 _reserved6[0x200 - 0x14C];
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u32 geni_cfg_reg64;
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u32 geni_cfg_reg65;
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u32 geni_cfg_reg66;
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u32 geni_cfg_reg67;
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u32 geni_cfg_reg68;
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u32 geni_cfg_reg69;
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u32 geni_cfg_reg70;
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u32 geni_cfg_reg71;
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u32 geni_cfg_reg72;
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u32 spi_cpha;
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u32 geni_cfg_reg74;
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u32 proto_loopback_cfg;
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u32 spi_cpol;
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u32 i2c_noise_cancellation_ctl;
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u32 i2c_monitor_ctl;
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u32 geni_cfg_reg79;
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u32 geni_cfg_reg80;
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u32 geni_cfg_reg81;
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u32 geni_cfg_reg82;
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u32 spi_demux_output_inv;
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u32 spi_demux_sel;
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u32 geni_byte_granularity;
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u32 geni_dma_mode_en;
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u32 uart_tx_trans_cfg_reg;
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u32 geni_tx_packing_cfg0;
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u32 geni_tx_packing_cfg1;
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union proto_word_len word_len;
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union proto_tx_trans_len tx_trans_len;
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union proto_rx_trans_len rx_trans_len;
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u32 spi_pre_post_cmd_dly;
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u32 i2c_scl_counters;
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u32 geni_cfg_reg95;
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u32 uart_rx_trans_cfg;
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u32 geni_rx_packing_cfg0;
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u32 geni_rx_packing_cfg1;
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u32 uart_rx_word_len;
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u32 geni_cfg_reg100;
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u32 uart_rx_stale_cnt;
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u32 geni_cfg_reg102;
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u32 geni_cfg_reg103;
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u32 geni_cfg_reg104;
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u32 uart_tx_parity_cfg;
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u32 uart_rx_parity_cfg;
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u32 uart_manual_rfr;
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u32 geni_cfg_reg108;
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u32 geni_cfg_reg109;
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u32 geni_cfg_reg110;
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u8 _reserved7[0x600 - 0x2BC];
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u32 geni_m_cmd0;
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u32 geni_m_cmd_ctrl_reg;
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u8 _reserved8[0x10 - 0x08];
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u32 geni_m_irq_status;
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u32 geni_m_irq_enable;
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u32 geni_m_irq_clear;
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u32 geni_m_irq_en_set;
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u32 geni_m_irq_en_clear;
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u32 geni_m_cmd_err_status;
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u32 geni_m_fw_err_status;
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u8 _reserved9[0x30 - 0x2C];
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u32 geni_s_cmd0;
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u32 geni_s_cmd_ctrl_reg;
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u8 _reserved10[0x40 - 0x38];
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u32 geni_s_irq_status;
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u32 geni_s_irq_enable;
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u32 geni_s_irq_clear;
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u32 geni_s_irq_en_set;
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u32 geni_s_irq_en_clear;
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u8 _reserved11[0x700 - 0x654];
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u32 geni_tx_fifon;
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u8 _reserved12[0x780 - 0x704];
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u32 geni_rx_fifon;
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u8 _reserved13[0x800 - 0x784];
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u32 geni_tx_fifo_status;
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u32 geni_rx_fifo_status;
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u32 geni_tx_fifo_threshold;
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u32 geni_tx_watermark_reg;
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u32 geni_rx_watermark_reg;
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u32 geni_rx_rfr_watermark_reg;
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u8 _reserved14[0x900 - 0x818];
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u32 geni_gp_output_reg;
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u8 _reserved15[0x908 - 0x904];
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u32 geni_ios;
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u32 geni_timestamp;
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u32 geni_m_gp_length;
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u32 geni_s_gp_length;
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u8 _reserved16[0x920 - 0x918];
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u32 geni_hw_irq_en;
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u32 geni_hw_irq_ignore_on_active;
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u8 _reserved17[0x930 - 0x928];
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u32 geni_hw_irq_cmd_param_0;
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u8 _reserved18[0xA00 - 0x934];
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u32 geni_i3c_ibi_cfg_tablen;
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u8 _reserved19[0xA80 - 0xA04];
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u32 geni_i3c_ibi_status;
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u32 geni_i3c_ibi_rd_data;
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u32 geni_i3c_ibi_search_pattern;
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u32 geni_i3c_ibi_search_data;
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u32 geni_i3c_sw_ibi_en;
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u32 geni_i3c_sw_ibi_en_recover;
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u8 _reserved20[0xC30 - 0xA98];
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u32 dma_tx_ptr_l;
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u32 dma_tx_ptr_h;
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u32 dma_tx_attr;
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u32 dma_tx_length;
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u32 dma_tx_irq_stat;
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u32 dma_tx_irq_clr;
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u32 dma_tx_irq_en;
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u32 dma_tx_irq_en_set;
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u32 dma_tx_irq_en_clr;
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u32 dma_tx_length_in;
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u32 dma_tx_fsm_rst;
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u32 dma_tx_max_burst_size;
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u8 _reserved21[0xD30 - 0xC60];
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u32 dma_rx_ptr_l;
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u32 dma_rx_ptr_h;
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u32 dma_rx_attr;
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u32 dma_rx_length;
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u32 dma_rx_irq_stat;
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u32 dma_rx_irq_clr;
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u32 dma_rx_irq_en;
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u32 dma_rx_irq_en_set;
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u32 dma_rx_irq_en_clr;
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u32 dma_rx_length_in;
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u32 dma_rx_fsm_rst;
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u32 dma_rx_max_burst_size;
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u32 dma_rx_flush;
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u8 _reserved22[0xE14 - 0xD64];
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u32 se_irq_high_priority;
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u32 se_gsi_event_en;
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u32 se_irq_en;
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u32 dma_if_en_ro;
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u32 se_hw_param_0;
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u32 se_hw_param_1;
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u32 se_hw_param_2;
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u32 dma_general_cfg;
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u8 _reserved23[0x40 - 0x34];
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u32 dma_debug_reg0;
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u32 dma_test_bus_ctrl;
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u32 se_top_test_bus_ctrl;
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u8 _reserved24[0x1000 - 0x0E4C];
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u32 se_geni_fw_revision;
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u32 se_s_fw_revision;
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u8 _reserved25[0x10-0x08];
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u32 se_geni_cfg_ramn;
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u8 _reserved26[0x2000 - 0x1014];
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u32 se_geni_clk_ctrl;
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u32 se_dma_if_en;
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u32 se_fifo_if_disable;
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u32 se_geni_fw_multilock_protns;
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u32 se_geni_fw_multilock_msa;
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u32 se_geni_fw_multilock_sp;
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};
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check_member(qup_regs, geni_clk_sel, 0x7C);
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check_member(qup_regs, geni_cfg_reg108, 0x2B0);
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check_member(qup_regs, geni_dma_mode_en, 0x258);
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check_member(qup_regs, geni_i3c_ibi_rd_data, 0xA84);
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check_member(qup_regs, dma_test_bus_ctrl, 0xE44);
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check_member(qup_regs, se_geni_cfg_ramn, 0x1010);
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check_member(qup_regs, se_geni_fw_multilock_sp, 0x2014);
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static struct console_input_driver consin = {
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.havekey = serial_havechar,
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.getchar = serial_getchar,
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.input_type = CONSOLE_INPUT_TYPE_UART,
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};
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static struct console_output_driver consout = {
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.putchar = serial_putchar,
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};
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static struct qup_regs *uart_base_address(void)
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{
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const struct cb_serial *const serial = phys_to_virt(lib_sysinfo.cb_serial);
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return phys_to_virt(serial->baseaddr);
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}
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static void uart_qupv3_tx_flush(void)
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{
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struct qup_regs *regs = uart_base_address();
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while (read32(®s->geni_status) & GENI_STATUS_M_GENI_CMD_ACTIVE_MASK)
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;
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}
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static unsigned char uart_qupv3_rx_byte(void)
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{
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struct qup_regs *regs = uart_base_address();
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if (read32(®s->geni_rx_fifo_status) & RX_FIFO_WC_MSK)
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return read32(®s->geni_rx_fifon) & 0xFF;
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return 0;
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}
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static void uart_qupv3_tx_byte(unsigned char data)
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{
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struct qup_regs *regs = uart_base_address();
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uart_qupv3_tx_flush();
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write32(®s->rx_trans_len.uart_tx_trans_len, 1);
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/* Start TX */
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write32(®s->geni_m_cmd0, START_UART_TX);
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write32(®s->geni_tx_fifon, data);
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}
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void serial_putchar(unsigned int data)
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{
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if (data == 0xa)
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uart_qupv3_tx_byte(0xd);
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uart_qupv3_tx_byte(data);
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}
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int serial_havechar(void)
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{
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struct qup_regs *regs = uart_base_address();
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if (read32(®s->geni_rx_fifo_status) & RX_FIFO_WC_MSK)
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return 1;
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return 0;
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}
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int serial_getchar(void)
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{
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return uart_qupv3_rx_byte();
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}
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void serial_console_init(void)
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{
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if (!lib_sysinfo.cb_serial)
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return;
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console_add_output_driver(&consout);
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console_add_input_driver(&consin);
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}
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