333 lines
8.2 KiB
C
333 lines
8.2 KiB
C
/*
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*
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* Copyright 2018 Google LLC
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <libpayload.h>
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#include <arch/apic.h>
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#include <arch/cpuid.h>
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#include <arch/msr.h>
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#include <exception.h>
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#define APIC_BASE_MSR 0x0000001B
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#define APIC_BASE_MASK (0xFFFFFFFULL << 12)
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#define CPUID_XAPIC_ENABLED_BIT (1 << 9)
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#define CPUID_XAPIC2_ENABLED_BIT (1 << 21)
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#define XAPIC_ENABLED_BIT (1 << 11)
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#define X2APIC_ENABLED_BIT (1 << 10)
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#define APIC_MASKED_BIT (1 << 16)
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#define APIC_ID 0x020
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#define APIC_ID_SHIFT 24
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#define APIC_ID_MASK (0xFFUL << APIC_ID_SHIFT)
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#define APIC_VERSION 0x030
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#define APIC_MAX_LVT_SHIFT 16
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#define APIC_MAX_LVT_MASK (0xFFUL << APIC_MAX_LVT_SHIFT)
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#define APIC_TASK_PRIORITY 0x080
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#define APIC_TASK_PRIORITY_MASK 0xFFUL
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#define APIC_EOI 0x0B0
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#define APIC_SPURIOUS 0x0F0
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#define APIC_SW_ENABLED_BIT (1 << 8)
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#define APIC_SPURIOUS_VECTOR_MASK 0xFFUL
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#define APIC_SPURIOUS 0x0F0
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#define APIC_LVT_TIMER 0x320
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#define APIC_TIMER_INIT_COUNT 0x380
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#define APIC_TIMER_CUR_COUNT 0x390
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#define APIC_TIMER_DIV_CFG 0x3E0
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#define APIC_ISR_0 0x100
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#define APIC_ISR_OFFSET 0x010
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#define APIC_LVT_SIZE 0x010
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#define APIC_TIMER_VECTOR 0x20UL
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#define APIC_SPURIOUS_VECTOR 0xFFUL
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static uint32_t apic_bar;
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static int _apic_initialized;
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// TODO: Build a lookup table to avoid calculating it.
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static uint32_t ticks_per_ms;
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static volatile uint8_t timer_waiting;
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enum APIC_CAPABILITY {
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DISABLED = 0,
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XACPI = 1 << 0,
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X2ACPI = 1 << 1
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};
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int apic_initialized(void)
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{
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return _apic_initialized;
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}
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static inline uint32_t apic_read32(uint32_t offset)
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{
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return read32((void *)(apic_bar + offset));
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}
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static inline void apic_write32(uint32_t offset, uint32_t value)
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{
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write32((void *)(apic_bar + offset), value);
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}
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uint8_t apic_id(void)
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{
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die_if(!apic_bar, "APIC is not initialized");
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uint8_t id =
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(apic_read32(APIC_ID) & APIC_ID_MASK) >> APIC_ID_SHIFT;
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return id;
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}
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void apic_start_delay(unsigned int usec)
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{
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die_if(!ticks_per_ms, "apic_init_timer was not run.");
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die_if(timer_waiting, "timer already started.");
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die_if(!interrupts_enabled(), "Interrupts disabled.");
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/* The order is important so we don't underflow */
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uint64_t ticks = usec * ticks_per_ms / USECS_PER_MSEC;
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/* Not enough resolution */
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if (!ticks)
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return;
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/* Disable interrupts so we don't get a race condition between
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* starting the timer and the hlt instruction. */
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disable_interrupts();
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timer_waiting = 1;
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apic_write32(APIC_TIMER_INIT_COUNT, ticks);
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enable_interrupts();
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}
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void apic_wait_delay(void)
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{
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/* Loop in case another interrupt has fired and resumed execution. */
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disable_interrupts();
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/* Note: when we test timer_waiting, interrupts are disabled by the line
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* above and the cli below. */
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while (timer_waiting) {
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asm volatile(
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"sti\n\t"
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"hlt\n\t"
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/* Disable interrupts to prevent a race condition
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* between checking timer_waiting and executing the hlt
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* instruction again. */
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"cli\n\t");
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}
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/* Leave hardware interrupts enabled. */
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enable_interrupts();
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}
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void apic_delay(unsigned int usec)
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{
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apic_start_delay(usec);
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apic_wait_delay();
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}
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static void timer_interrupt_handler(u8 vector)
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{
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timer_waiting = 0;
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apic_eoi(APIC_TIMER_VECTOR);
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}
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static void suprious_interrupt_handler(u8 vector) {}
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void apic_eoi(uint8_t vector)
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{
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die_if(!apic_bar, "APIC is not initialized");
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/*
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* Local and I/O APICs support 240 vectors (in the range of 16 to 255)
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* as valid interrupts.
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*/
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if (vector <= 15)
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return;
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/* Each bank handles 32 vectors */
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uint8_t bank = vector / 32;
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uint32_t offset = APIC_ISR_0 + bank * APIC_ISR_OFFSET;
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uint32_t mask = apic_read32(offset);
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uint8_t shift = vector % 32;
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if (mask & (1 << shift))
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apic_write32(APIC_EOI, 0);
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}
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static enum APIC_CAPABILITY apic_capabilities(void)
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{
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uint32_t eax, ebx, ecx, edx;
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cpuid(1, eax, ebx, ecx, edx);
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enum APIC_CAPABILITY capabilities = DISABLED;
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if (edx & CPUID_XAPIC_ENABLED_BIT)
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capabilities |= XACPI;
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if (ecx & CPUID_XAPIC2_ENABLED_BIT)
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capabilities |= X2ACPI;
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return capabilities;
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}
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static uint8_t apic_max_lvt_entries(void)
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{
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die_if(!apic_bar, "APIC is not initialized");
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uint32_t reg = apic_read32(APIC_VERSION);
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reg &= APIC_MAX_LVT_MASK;
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reg >>= APIC_MAX_LVT_SHIFT;
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return (uint8_t)reg;
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}
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static void apic_reset_all_lvts(void)
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{
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uint8_t max = apic_max_lvt_entries();
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for (int i = 0; i <= max; ++i) {
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uint32_t offset = APIC_LVT_TIMER + APIC_LVT_SIZE * i;
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apic_eoi(i);
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apic_write32(offset, APIC_MASKED_BIT);
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}
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}
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static void apic_set_task_priority(uint8_t priority)
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{
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die_if(!apic_bar, "APIC is not initialized");
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uint32_t tpr = apic_read32(APIC_TASK_PRIORITY);
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tpr &= ~APIC_TASK_PRIORITY_MASK;
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tpr |= priority;
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apic_write32(APIC_TASK_PRIORITY, priority);
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}
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static void apic_init_timer(void)
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{
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die_if(!apic_bar, "APIC is not initialized");
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apic_write32(APIC_LVT_TIMER, APIC_MASKED_BIT);
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/* Divide the clock by 1. */
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apic_write32(APIC_TIMER_DIV_CFG, 0xB);
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/* Calibrate the APIC timer */
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if (!ticks_per_ms) {
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/* Set APIC init counter to MAX and count for 1 ms */
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apic_write32(APIC_TIMER_INIT_COUNT, UINT32_MAX);
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/* This is safe because apic_initialized() returns false so
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* arch_ndelay() falls back to a busy loop. */
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mdelay(1);
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ticks_per_ms =
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UINT32_MAX - apic_read32(APIC_TIMER_CUR_COUNT);
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}
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/* Clear the count so we don't get any stale interrupts */
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apic_write32(APIC_TIMER_INIT_COUNT, 0);
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/* Unmask the timer and set the vector. */
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apic_write32(APIC_LVT_TIMER, APIC_TIMER_VECTOR);
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}
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static void apic_sw_disable(void)
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{
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uint32_t reg = apic_read32(APIC_SPURIOUS);
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reg &= ~APIC_SW_ENABLED_BIT;
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printf("%s: writing %#x to %#x\n", __func__, reg, APIC_SPURIOUS);
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apic_write32(APIC_SPURIOUS, reg);
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}
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static void apic_sw_enable(void)
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{
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uint32_t reg = apic_read32(APIC_SPURIOUS);
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if (reg & APIC_SW_ENABLED_BIT)
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return;
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reg |= APIC_SW_ENABLED_BIT;
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apic_write32(APIC_SPURIOUS, reg);
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}
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static void apic_setup_spurious(void)
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{
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uint32_t reg = apic_read32(APIC_SPURIOUS);
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reg &= ~APIC_SPURIOUS_VECTOR_MASK;
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reg |= APIC_SPURIOUS_VECTOR;
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apic_write32(APIC_SPURIOUS, reg);
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}
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void apic_init(void)
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{
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uint64_t apic_bar_reg;
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printf("APIC Init Started\n");
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die_if(apic_initialized(), "APIC already initialized");
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die_if(!(apic_capabilities() & XACPI), "APIC is not supported");
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apic_bar_reg = _rdmsr(APIC_BASE_MSR);
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printf("apic_bar_reg is 0x%llx\n", apic_bar_reg);
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die_if(!(apic_bar_reg & XAPIC_ENABLED_BIT), "APIC is not enabled");
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die_if(apic_bar_reg & X2APIC_ENABLED_BIT,
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"APIC is configured in x2APIC mode which is not supported");
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apic_bar = (uint32_t)(apic_bar_reg & APIC_BASE_MASK);
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apic_sw_disable();
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apic_reset_all_lvts();
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apic_set_task_priority(0);
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apic_setup_spurious();
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apic_sw_enable();
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apic_init_timer();
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set_interrupt_handler(APIC_TIMER_VECTOR, &timer_interrupt_handler);
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set_interrupt_handler(APIC_SPURIOUS_VECTOR,
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&suprious_interrupt_handler);
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_apic_initialized = 1;
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printf("APIC Configured\n");
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}
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