550 lines
13 KiB
C
550 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <types.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <device/pci_def.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/em64t101_save_state.h>
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#include <elog.h>
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#include <halt.h>
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#include <option.h>
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#include <southbridge/intel/common/finalize.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <smmstore.h>
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#include "me.h"
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#include "pch.h"
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#include "nvs.h"
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static u8 smm_initialized = 0;
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int southbridge_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x32:
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printk(BIOS_DEBUG, "OS Init\n");
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/* gnvs->smif:
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* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*/
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gnvs->smif = 0;
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return 1; /* IO trap handled */
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}
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/* Not handled */
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return 0;
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}
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/**
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* @brief Set the EOS bit
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*/
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void southbridge_smi_set_eos(void)
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{
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enable_smi(EOS);
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}
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static void busmaster_disable_on_bus(int bus)
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{
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int slot, func;
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unsigned int val;
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unsigned char hdr;
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for (slot = 0; slot < 0x20; slot++) {
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for (func = 0; func < 8; func++) {
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u16 reg16;
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pci_devfn_t dev = PCI_DEV(bus, slot, func);
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val = pci_read_config32(dev, PCI_VENDOR_ID);
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if (val == 0xffffffff || val == 0x00000000 ||
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val == 0x0000ffff || val == 0xffff0000)
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continue;
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/* Disable Bus Mastering for this one device */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MASTER;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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/* If this is a bridge, then follow it. */
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hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
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hdr &= 0x7f;
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if (hdr == PCI_HEADER_TYPE_BRIDGE ||
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hdr == PCI_HEADER_TYPE_CARDBUS) {
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unsigned int buses;
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buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
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busmaster_disable_on_bus((buses >> 8) & 0xff);
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}
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}
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}
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}
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static void southbridge_smi_sleep(void)
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{
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u8 reg8;
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u32 reg32;
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u8 slp_typ;
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u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
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u16 pmbase = get_pmbase();
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// save and recover RTC port values
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u8 tmp70, tmp72;
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tmp70 = inb(0x70);
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tmp72 = inb(0x72);
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get_option(&s5pwr, "power_on_after_fail");
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outb(tmp70, 0x70);
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outb(tmp72, 0x72);
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/* First, disable further SMIs */
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disable_smi(SLP_SMI_EN);
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/* Figure out SLP_TYP */
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reg32 = inl(pmbase + PM1_CNT);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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slp_typ = acpi_sleep_from_pm1(reg32);
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/* Do any mainboard sleep handling */
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mainboard_smi_sleep(slp_typ);
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/* USB sleep preparations */
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#if !CONFIG(FINALIZE_USB_ROUTE_XHCI)
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usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ);
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usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ);
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#endif
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usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ);
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/* Log S3, S4, and S5 entry */
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if (slp_typ >= ACPI_S3)
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elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
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/* Next, do the deed.
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*/
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switch (slp_typ) {
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case ACPI_S0:
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printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
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break;
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case ACPI_S1:
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printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
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break;
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case ACPI_S3:
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printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
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/* Invalidate the cache before going to S3 */
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wbinvd();
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break;
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case ACPI_S4:
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printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
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break;
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case ACPI_S5:
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printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
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/* Disable all GPE */
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disable_all_gpe();
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/* Always set the flag in case CMOS was changed on runtime. For
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* "KEEP", switch to "OFF" - KEEP is software emulated
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*/
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
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if (s5pwr == MAINBOARD_POWER_ON) {
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reg8 &= ~1;
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} else {
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reg8 |= 1;
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}
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
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/* also iterates over all bridges on bus 0 */
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busmaster_disable_on_bus(0);
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break;
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default:
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printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
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break;
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}
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/* Write back to the SLP register to cause the originally intended
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* event again. We need to set BIT13 (SLP_EN) though to make the
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* sleep happen.
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*/
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enable_pm1_control(SLP_EN);
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/* Make sure to stop executing code here for S3/S4/S5 */
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if (slp_typ >= ACPI_S3)
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halt();
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/* In most sleep states, the code flow of this function ends at
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* the line above. However, if we entered sleep state S1 and wake
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* up again, we will continue to execute code in this function.
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*/
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reg32 = inl(pmbase + PM1_CNT);
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if (reg32 & SCI_EN) {
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/* The OS is not an ACPI OS, so we set the state to S0 */
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disable_pm1_control(SLP_EN | SLP_TYP);
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}
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}
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/*
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* Look for Synchronous IO SMI and use save state from that
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* core in case we are not running on the same core that
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* initiated the IO transaction.
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*/
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static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
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{
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em64t101_smm_state_save_area_t *state;
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int node;
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/* Check all nodes looking for the one that issued the IO */
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for (node = 0; node < CONFIG_MAX_CPUS; node++) {
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state = smm_get_save_state(node);
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/* Check for Synchronous IO (bit0 == 1) */
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if (!(state->io_misc_info & (1 << 0)))
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continue;
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/* Make sure it was a write (bit4 == 0) */
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if (state->io_misc_info & (1 << 4))
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continue;
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/* Check for APMC IO port */
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if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
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continue;
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/* Check AX against the requested command */
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if ((state->rax & 0xff) != cmd)
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continue;
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return state;
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}
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return NULL;
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}
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static void southbridge_smi_gsmi(void)
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{
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u32 *ret, *param;
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u8 sub_command;
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em64t101_smm_state_save_area_t *io_smi =
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smi_apmc_find_state_save(APM_CNT_ELOG_GSMI);
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if (!io_smi)
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return;
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/* Command and return value in EAX */
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ret = (u32*)&io_smi->rax;
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sub_command = (u8)(*ret >> 8);
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/* Parameter buffer in EBX */
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param = (u32*)&io_smi->rbx;
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/* drivers/elog/gsmi.c */
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*ret = gsmi_exec(sub_command, param);
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}
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static void southbridge_smi_store(void)
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{
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u8 sub_command, ret;
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em64t101_smm_state_save_area_t *io_smi =
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smi_apmc_find_state_save(APM_CNT_SMMSTORE);
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uint32_t reg_ebx;
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if (!io_smi)
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return;
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/* Command and return value in EAX */
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sub_command = (io_smi->rax >> 8) & 0xff;
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/* Parameter buffer in EBX */
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reg_ebx = io_smi->rbx;
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/* drivers/smmstore/smi.c */
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ret = smmstore_exec(sub_command, (void *)reg_ebx);
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io_smi->rax = ret;
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}
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static void southbridge_smi_apmc(void)
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{
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u8 reg8;
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em64t101_smm_state_save_area_t *state;
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static int chipset_finalized = 0;
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/* Emulate B2 register as the FADT / Linux expects it */
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reg8 = inb(APM_CNT);
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switch (reg8) {
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case APM_CNT_FINALIZE:
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if (chipset_finalized) {
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printk(BIOS_DEBUG, "SMI#: Already finalized\n");
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return;
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}
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intel_me_finalize_smm();
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intel_pch_finalize_smm();
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intel_northbridge_haswell_finalize_smm();
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intel_cpu_haswell_finalize_smm();
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chipset_finalized = 1;
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break;
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case APM_CNT_CST_CONTROL:
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/* Calling this function seems to cause
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* some kind of race condition in Linux
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* and causes a kernel oops
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*/
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printk(BIOS_DEBUG, "C-state control\n");
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break;
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case APM_CNT_PST_CONTROL:
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/* Calling this function seems to cause
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* some kind of race condition in Linux
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* and causes a kernel oops
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*/
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printk(BIOS_DEBUG, "P-state control\n");
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break;
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case APM_CNT_ACPI_DISABLE:
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disable_pm1_control(SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
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break;
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case APM_CNT_ACPI_ENABLE:
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enable_pm1_control(SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
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break;
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case APM_CNT_GNVS_UPDATE:
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if (smm_initialized) {
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printk(BIOS_DEBUG,
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"SMI#: SMM structures already initialized!\n");
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return;
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}
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state = smi_apmc_find_state_save(reg8);
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if (state) {
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/* EBX in the state save contains the GNVS pointer */
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gnvs = (struct global_nvs *)((u32)state->rbx);
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smm_initialized = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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break;
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case APM_CNT_ROUTE_ALL_XHCI:
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usb_xhci_route_all();
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break;
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case APM_CNT_ELOG_GSMI:
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if (CONFIG(ELOG_GSMI))
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southbridge_smi_gsmi();
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break;
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case APM_CNT_SMMSTORE:
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if (CONFIG(SMMSTORE))
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southbridge_smi_store();
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break;
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}
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mainboard_smi_apmc(reg8);
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}
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static void southbridge_smi_pm1(void)
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{
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u16 pm1_sts = clear_pm1_status();
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/* While OSPM is not active, poweroff immediately
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* on a power button event.
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*/
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if (pm1_sts & PWRBTN_STS) {
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// power button pressed
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elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
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disable_pm1_control(-1UL);
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enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
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}
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}
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static void southbridge_smi_gpe0(void)
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{
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clear_gpe_status();
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}
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static void southbridge_smi_gpi(void)
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{
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mainboard_smi_gpi(clear_alt_smi_status());
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/* Clear again after mainboard handler */
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clear_alt_smi_status();
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}
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static void southbridge_smi_mc(void)
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{
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u32 reg32;
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reg32 = inl(get_pmbase() + SMI_EN);
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/* Are microcontroller SMIs enabled? */
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if ((reg32 & MCSMI_EN) == 0)
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return;
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printk(BIOS_DEBUG, "Microcontroller SMI.\n");
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}
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static void southbridge_smi_tco(void)
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{
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u32 tco_sts = clear_tco_status();
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/* Any TCO event? */
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if (!tco_sts)
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return;
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if (tco_sts & (1 << 8)) { // BIOSWR
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u8 bios_cntl;
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bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
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if (bios_cntl & 1) {
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/* BWE is RW, so the SMI was caused by a
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* write to BWE, not by a write to the BIOS
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*/
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/* This is the place where we notice someone
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* is trying to tinker with the BIOS. We are
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* trying to be nice and just ignore it. A more
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* resolute answer would be to power down the
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc,
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(bios_cntl & ~1));
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} /* No else for now? */
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} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
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/* Handle TCO timeout */
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printk(BIOS_DEBUG, "TCO Timeout.\n");
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}
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}
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static void southbridge_smi_periodic(void)
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{
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u32 reg32;
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reg32 = inl(get_pmbase() + SMI_EN);
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/* Are periodic SMIs enabled? */
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if ((reg32 & PERIODIC_EN) == 0)
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return;
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printk(BIOS_DEBUG, "Periodic SMI.\n");
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}
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static void southbridge_smi_monitor(void)
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{
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#define IOTRAP(x) (trap_sts & (1 << x))
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u32 trap_sts, trap_cycle;
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u32 data, mask = 0;
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int i;
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trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
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RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
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trap_cycle = RCBA32(0x1e10);
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for (i=16; i<20; i++) {
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if (trap_cycle & (1 << i))
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mask |= (0xff << ((i - 16) << 2));
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}
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/* IOTRAP(3) SMI function call */
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if (IOTRAP(3)) {
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if (gnvs && gnvs->smif)
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io_trap_handler(gnvs->smif); // call function smif
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return;
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}
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/* IOTRAP(2) currently unused
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* IOTRAP(1) currently unused */
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/* IOTRAP(0) SMIC */
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if (IOTRAP(0)) {
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if (!(trap_cycle & (1 << 24))) { // It's a write
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printk(BIOS_DEBUG, "SMI1 command\n");
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data = RCBA32(0x1e18);
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data &= mask;
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// if (smi1)
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// southbridge_smi_command(data);
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// return;
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}
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// Fall through to debug
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}
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printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
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trap_cycle & 0xfffc);
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for (i=0; i < 4; i++)
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if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
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printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
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printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
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printk(BIOS_DEBUG, " read/write: %s\n",
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(trap_cycle & (1 << 24)) ? "read" : "write");
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if (!(trap_cycle & (1 << 24))) {
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/* Write Cycle */
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data = RCBA32(0x1e18);
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printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
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}
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#undef IOTRAP
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}
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typedef void (*smi_handler_t)(void);
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static smi_handler_t southbridge_smi[32] = {
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NULL, // [0] reserved
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NULL, // [1] reserved
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NULL, // [2] BIOS_STS
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NULL, // [3] LEGACY_USB_STS
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southbridge_smi_sleep, // [4] SLP_SMI_STS
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southbridge_smi_apmc, // [5] APM_STS
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NULL, // [6] SWSMI_TMR_STS
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NULL, // [7] reserved
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southbridge_smi_pm1, // [8] PM1_STS
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southbridge_smi_gpe0, // [9] GPE0_STS
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southbridge_smi_gpi, // [10] GPI_STS
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southbridge_smi_mc, // [11] MCSMI_STS
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NULL, // [12] DEVMON_STS
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southbridge_smi_tco, // [13] TCO_STS
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southbridge_smi_periodic, // [14] PERIODIC_STS
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NULL, // [15] SERIRQ_SMI_STS
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NULL, // [16] SMBUS_SMI_STS
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NULL, // [17] LEGACY_USB2_STS
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|
NULL, // [18] INTEL_USB2_STS
|
|
NULL, // [19] reserved
|
|
NULL, // [20] PCI_EXP_SMI_STS
|
|
southbridge_smi_monitor, // [21] MONITOR_STS
|
|
NULL, // [22] reserved
|
|
NULL, // [23] reserved
|
|
NULL, // [24] reserved
|
|
NULL, // [25] EL_SMI_STS
|
|
NULL, // [26] SPI_STS
|
|
NULL, // [27] reserved
|
|
NULL, // [28] reserved
|
|
NULL, // [29] reserved
|
|
NULL, // [30] reserved
|
|
NULL // [31] reserved
|
|
};
|
|
|
|
/**
|
|
* @brief Interrupt handler for SMI#
|
|
*/
|
|
void southbridge_smi_handler(void)
|
|
{
|
|
int i;
|
|
u32 smi_sts;
|
|
|
|
/* We need to clear the SMI status registers, or we won't see what's
|
|
* happening in the following calls.
|
|
*/
|
|
smi_sts = clear_smi_status();
|
|
|
|
/* Call SMI sub handler for each of the status bits */
|
|
for (i = 0; i < 31; i++) {
|
|
if (smi_sts & (1 << i)) {
|
|
if (southbridge_smi[i]) {
|
|
southbridge_smi[i]();
|
|
} else {
|
|
printk(BIOS_DEBUG,
|
|
"SMI_STS[%d] occurred, but no "
|
|
"handler available.\n", i);
|
|
}
|
|
}
|
|
}
|
|
}
|