206 lines
5.0 KiB
C
206 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <types.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/em64t101_save_state.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/me.h>
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#include <southbridge/intel/common/gpio.h>
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#include <cpu/intel/model_206ax/model_206ax.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <southbridge/intel/common/finalize.h>
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#include "pch.h"
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#include "nvs.h"
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int southbridge_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x32:
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printk(BIOS_DEBUG, "OS Init\n");
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/* gnvs->smif:
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* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*/
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gnvs->smif = 0;
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return 1; /* IO trap handled */
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}
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/* Not handled */
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return 0;
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}
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static void southbridge_gate_memory_reset_real(int offset,
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u16 use, u16 io, u16 lvl)
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{
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u32 reg32;
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/* Make sure it is set as GPIO */
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reg32 = inl(use);
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if (!(reg32 & (1 << offset))) {
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reg32 |= (1 << offset);
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outl(reg32, use);
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}
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/* Make sure it is set as output */
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reg32 = inl(io);
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if (reg32 & (1 << offset)) {
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reg32 &= ~(1 << offset);
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outl(reg32, io);
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}
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/* Drive the output low */
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reg32 = inl(lvl);
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reg32 &= ~(1 << offset);
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outl(reg32, lvl);
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}
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/*
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* Drive GPIO 60 low to gate memory reset in S3.
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*
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* Intel reference designs all use GPIO 60 but it is
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* not a requirement and boards could use a different pin.
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*/
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void southbridge_gate_memory_reset(void)
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{
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u16 gpiobase;
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gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
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if (!gpiobase)
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return;
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if (CONFIG_DRAM_RESET_GATE_GPIO >= 32)
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southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32,
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gpiobase + GPIO_USE_SEL2,
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gpiobase + GP_IO_SEL2,
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gpiobase + GP_LVL2);
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else
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southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO,
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gpiobase + GPIO_USE_SEL,
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gpiobase + GP_IO_SEL,
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gpiobase + GP_LVL);
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}
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static void xhci_sleep(u8 slp_typ)
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{
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u32 xhci_bar;
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u16 reg16;
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switch (slp_typ) {
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case ACPI_S3:
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case ACPI_S4:
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/* FIXME: Unbalanced width in read/write ops (16-bit read then 32-bit write) */
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reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
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reg16 &= ~0x03UL;
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pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
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pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND,
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL;
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if ((xhci_bar + 0x4C0) & 1)
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pch_iobp_update(0xEC000082, ~0UL, (3 << 2));
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if ((xhci_bar + 0x4D0) & 1)
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pch_iobp_update(0xEC000182, ~0UL, (3 << 2));
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if ((xhci_bar + 0x4E0) & 1)
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pch_iobp_update(0xEC000282, ~0UL, (3 << 2));
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if ((xhci_bar + 0x4F0) & 1)
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pch_iobp_update(0xEC000382, ~0UL, (3 << 2));
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pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND,
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~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
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pci_or_config16(PCH_XHCI_DEV, 0x74, 0x03);
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break;
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case ACPI_S5:
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pci_or_config16(PCH_XHCI_DEV, 0x74, (1 << 8) | 0x03);
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break;
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}
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}
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void southbridge_smi_monitor(void)
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{
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#define IOTRAP(x) (trap_sts & (1 << x))
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u32 trap_sts, trap_cycle;
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u32 data, mask = 0;
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int i;
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trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
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RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
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trap_cycle = RCBA32(0x1e10);
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for (i=16; i<20; i++) {
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if (trap_cycle & (1 << i))
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mask |= (0xff << ((i - 16) << 2));
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}
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/* IOTRAP(3) SMI function call */
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if (IOTRAP(3)) {
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if (gnvs && gnvs->smif)
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io_trap_handler(gnvs->smif); // call function smif
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return;
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}
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/* IOTRAP(2) currently unused
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* IOTRAP(1) currently unused */
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/* IOTRAP(0) SMIC */
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if (IOTRAP(0)) {
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if (!(trap_cycle & (1 << 24))) { // It's a write
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printk(BIOS_DEBUG, "SMI1 command\n");
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data = RCBA32(0x1e18);
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data &= mask;
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// if (smi1)
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// southbridge_smi_command(data);
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// return;
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}
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// Fall through to debug
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}
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printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
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for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
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printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
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printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
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printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
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if (!(trap_cycle & (1 << 24))) {
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/* Write Cycle */
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data = RCBA32(0x1e18);
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printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
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}
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#undef IOTRAP
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}
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void southbridge_smm_xhci_sleep(u8 slp_type)
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{
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if (gnvs->xhci)
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xhci_sleep(slp_type);
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}
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void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
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{
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em64t101_smm_state_save_area_t *state =
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smi_apmc_find_state_save(apm_cnt);
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if (state) {
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/* EBX in the state save contains the GNVS pointer */
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gnvs = (struct global_nvs *)((u32)state->rbx);
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*smm_done = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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}
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void southbridge_finalize_all(void)
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{
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intel_me_finalize_smm();
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intel_pch_finalize_smm();
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intel_sandybridge_finalize_smm();
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intel_model_206ax_finalize_smm();
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}
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