641 lines
15 KiB
C
641 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/hlt.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/em64t100_save_state.h>
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#include <cpu/intel/em64t101_save_state.h>
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#include <delay.h>
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#include <device/pci_def.h>
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#include <elog.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/smihandler.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/uart.h>
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#include <smmstore.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/smbus.h>
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#include <spi-generic.h>
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#include <stdint.h>
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/* SoC overrides. */
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__weak const struct smm_save_state_ops *get_smm_save_state_ops(void)
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{
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return &em64t101_smm_ops;
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}
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/* Specific SOC SMI handler during ramstage finalize phase */
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__weak void smihandler_soc_at_finalize(void)
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{
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return;
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}
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__weak int smihandler_soc_disable_busmaster(pci_devfn_t dev)
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{
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return 1;
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}
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/*
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* Needs to implement the mechanism to know if an illegal attempt
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* has been made to write to the BIOS area.
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*/
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static void smihandler_soc_check_illegal_access(
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uint32_t tco_sts)
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{
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if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
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&& fast_spi_wpd_status()))
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return;
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/*
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* BWE is RW, so the SMI was caused by a
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* write to BWE, not by a write to the BIOS
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*
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* This is the place where we notice someone
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* is trying to tinker with the BIOS. We are
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* trying to be nice and just ignore it. A more
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* resolute answer would be to power down the
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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fast_spi_enable_wp();
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}
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/* Mainboard overrides. */
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__weak void mainboard_smi_gpi_handler(
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const struct gpi_status *sts)
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{
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return;
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}
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__weak void mainboard_smi_espi_handler(void)
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{
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return;
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}
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/* Common Functions */
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static void *find_save_state(const struct smm_save_state_ops *save_state_ops,
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int cmd)
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{
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int node;
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void *state = NULL;
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uint32_t io_misc_info;
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uint8_t reg_al;
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/* Check all nodes looking for the one that issued the IO */
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for (node = 0; node < CONFIG_MAX_CPUS; node++) {
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state = smm_get_save_state(node);
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io_misc_info = save_state_ops->get_io_misc_info(state);
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/* Check for Synchronous IO (bit0==1) */
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if (!(io_misc_info & (1 << 0)))
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continue;
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/* Make sure it was a write (bit4==0) */
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if (io_misc_info & (1 << 4))
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continue;
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/* Check for APMC IO port */
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if (((io_misc_info >> 16) & 0xff) != APM_CNT)
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continue;
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/* Check AL against the requested command */
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reg_al = save_state_ops->get_reg(state, RAX);
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if (reg_al != cmd)
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continue;
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break;
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}
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return state;
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}
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/* Inherited from cpu/x86/smm.h resulting in a different signature */
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void southbridge_smi_set_eos(void)
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{
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pmc_enable_smi(EOS);
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}
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static void busmaster_disable_on_bus(int bus)
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{
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int slot, func;
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unsigned int val;
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unsigned char hdr;
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for (slot = 0; slot < 0x20; slot++) {
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for (func = 0; func < 8; func++) {
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u16 reg16;
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pci_devfn_t dev = PCI_DEV(bus, slot, func);
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if (!smihandler_soc_disable_busmaster(dev))
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continue;
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val = pci_read_config32(dev, PCI_VENDOR_ID);
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if (val == 0xffffffff || val == 0x00000000 ||
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val == 0x0000ffff || val == 0xffff0000)
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continue;
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/* Disable Bus Mastering for this one device */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MASTER;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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/* If it's not a bridge, move on. */
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hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
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hdr &= 0x7f;
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if (hdr != PCI_HEADER_TYPE_BRIDGE &&
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hdr != PCI_HEADER_TYPE_CARDBUS)
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continue;
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/*
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* If secondary bus is equal to current bus bypass
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* the bridge because it's likely unconfigured and
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* would cause infinite recursion.
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*/
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int secbus = pci_read_config8(dev, PCI_SECONDARY_BUS);
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if (secbus == bus)
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continue;
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busmaster_disable_on_bus(secbus);
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}
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}
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}
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void smihandler_southbridge_sleep(
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const struct smm_save_state_ops *save_state_ops)
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{
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uint32_t reg32;
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uint8_t slp_typ;
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/* First, disable further SMIs */
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pmc_disable_smi(SLP_SMI_EN);
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/* Figure out SLP_TYP */
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reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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slp_typ = acpi_sleep_from_pm1(reg32);
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/* Do any mainboard sleep handling */
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mainboard_smi_sleep(slp_typ);
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/* Log S3, S4, and S5 entry */
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if (slp_typ >= ACPI_S3)
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elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
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/* Clear pending GPE events */
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pmc_clear_all_gpe_status();
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/* Next, do the deed. */
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switch (slp_typ) {
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case ACPI_S0:
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printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
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break;
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case ACPI_S3:
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printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
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gnvs->uior = uart_is_controller_initialized();
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/* Invalidate the cache before going to S3 */
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wbinvd();
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break;
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case ACPI_S4:
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printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
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break;
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case ACPI_S5:
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printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
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/* Disable all GPE */
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pmc_disable_all_gpe();
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/* Set which state system will be after power reapplied */
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pmc_set_power_failure_state(false);
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/* also iterates over all bridges on bus 0 */
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busmaster_disable_on_bus(0);
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/*
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* Some platforms (e.g. Chromebooks) have observed race between
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* SLP SMI and PWRBTN SMI because of the way these SMIs are
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* triggered on power button press. Allow adding a delay before
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* triggering sleep enable for S5, so that power button
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* interrupt does not result into immediate wake.
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*/
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mdelay(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS);
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/*
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* Ensure any pending power button status bits are cleared as
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* the system is entering S5 and doesn't want to be woken up
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* right away from older power button events.
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*/
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pmc_clear_pm1_status();
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break;
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default:
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printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
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break;
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}
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/* Tri-state specific GPIOS to avoid leakage during S3/S5 */
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/*
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* Write back to the SLP register to cause the originally intended
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* event again. We need to set BIT13 (SLP_EN) though to make the
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* sleep happen.
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*/
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pmc_enable_pm1_control(SLP_EN);
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/* Make sure to stop executing code here for S3/S4/S5 */
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if (slp_typ >= ACPI_S3)
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hlt();
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/*
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* In most sleep states, the code flow of this function ends at
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* the line above. However, if we entered sleep state S1 and wake
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* up again, we will continue to execute code in this function.
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*/
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if (pmc_read_pm1_control() & SCI_EN) {
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/* The OS is not an ACPI OS, so we set the state to S0 */
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pmc_disable_pm1_control(SLP_EN | SLP_TYP);
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}
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}
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static void southbridge_smi_gsmi(
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const struct smm_save_state_ops *save_state_ops)
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{
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u8 sub_command, ret;
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void *io_smi = NULL;
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uint32_t reg_ebx;
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io_smi = find_save_state(save_state_ops, APM_CNT_ELOG_GSMI);
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if (!io_smi)
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return;
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/* Command and return value in EAX */
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sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8)
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& 0xff;
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/* Parameter buffer in EBX */
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reg_ebx = save_state_ops->get_reg(io_smi, RBX);
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/* drivers/elog/gsmi.c */
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ret = gsmi_exec(sub_command, ®_ebx);
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save_state_ops->set_reg(io_smi, RAX, ret);
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}
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static void southbridge_smi_store(
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const struct smm_save_state_ops *save_state_ops)
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{
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u8 sub_command, ret;
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void *io_smi;
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uint32_t reg_ebx;
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io_smi = find_save_state(save_state_ops, APM_CNT_SMMSTORE);
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if (!io_smi)
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return;
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/* Command and return value in EAX */
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sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) & 0xff;
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/* Parameter buffer in EBX */
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reg_ebx = save_state_ops->get_reg(io_smi, RBX);
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/* drivers/smmstore/smi.c */
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ret = smmstore_exec(sub_command, (void *)reg_ebx);
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save_state_ops->set_reg(io_smi, RAX, ret);
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}
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static void finalize(void)
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{
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static int finalize_done;
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if (finalize_done) {
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printk(BIOS_DEBUG, "SMM already finalized.\n");
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return;
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}
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finalize_done = 1;
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if (CONFIG(SPI_FLASH_SMM))
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/* Re-init SPI driver to handle locked BAR */
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fast_spi_init();
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/* Specific SOC SMI handler during ramstage finalize phase */
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smihandler_soc_at_finalize();
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}
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void smihandler_southbridge_apmc(
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const struct smm_save_state_ops *save_state_ops)
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{
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uint8_t reg8;
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void *state = NULL;
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static int smm_initialized = 0;
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/* Emulate B2 register as the FADT / Linux expects it */
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reg8 = inb(APM_CNT);
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switch (reg8) {
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case APM_CNT_CST_CONTROL:
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/*
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* Calling this function seems to cause
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* some kind of race condition in Linux
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* and causes a kernel oops
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*/
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printk(BIOS_DEBUG, "C-state control\n");
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break;
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case APM_CNT_PST_CONTROL:
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/*
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* Calling this function seems to cause
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* some kind of race condition in Linux
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* and causes a kernel oops
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*/
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printk(BIOS_DEBUG, "P-state control\n");
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break;
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case APM_CNT_ACPI_DISABLE:
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pmc_disable_pm1_control(SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
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break;
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case APM_CNT_ACPI_ENABLE:
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pmc_enable_pm1_control(SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
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break;
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case APM_CNT_GNVS_UPDATE:
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if (smm_initialized) {
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printk(BIOS_DEBUG,
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"SMI#: SMM structures already initialized!\n");
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return;
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}
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state = find_save_state(save_state_ops, reg8);
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if (state) {
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/* EBX in the state save contains the GNVS pointer */
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uint32_t reg_ebx = save_state_ops->get_reg(state, RBX);
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gnvs = (struct global_nvs *)(uintptr_t)reg_ebx;
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smm_initialized = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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break;
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case APM_CNT_ELOG_GSMI:
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if (CONFIG(ELOG_GSMI))
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southbridge_smi_gsmi(save_state_ops);
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break;
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case APM_CNT_SMMSTORE:
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if (CONFIG(SMMSTORE))
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southbridge_smi_store(save_state_ops);
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break;
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case APM_CNT_FINALIZE:
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finalize();
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break;
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}
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mainboard_smi_apmc(reg8);
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}
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void smihandler_southbridge_pm1(
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const struct smm_save_state_ops *save_state_ops)
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{
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uint16_t pm1_sts = pmc_clear_pm1_status();
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u16 pm1_en = pmc_read_pm1_enable();
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/*
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* While OSPM is not active, poweroff immediately
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* on a power button event.
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*/
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if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) {
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/* power button pressed */
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elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
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pmc_disable_pm1_control(-1UL);
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pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
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}
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}
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void smihandler_southbridge_gpe0(
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const struct smm_save_state_ops *save_state_ops)
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{
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pmc_clear_all_gpe_status();
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}
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void smihandler_southbridge_tco(
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const struct smm_save_state_ops *save_state_ops)
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{
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uint32_t tco_sts = pmc_clear_tco_status();
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/* Any TCO event? */
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if (!tco_sts)
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return;
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smihandler_soc_check_illegal_access(tco_sts);
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if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */
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/* Handle TCO timeout */
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printk(BIOS_DEBUG, "TCO Timeout.\n");
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}
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if (tco_sts & (TCO_INTRD_DET << 16)) { /* INTRUDER# assertion */
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/*
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* Handle intrusion event
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* If we ever get here, probably the case has been opened.
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*/
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printk(BIOS_CRIT, "Case intrusion detected.\n");
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}
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}
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void smihandler_southbridge_periodic(
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const struct smm_save_state_ops *save_state_ops)
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{
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uint32_t reg32;
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reg32 = pmc_get_smi_en();
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/* Are periodic SMIs enabled? */
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if ((reg32 & PERIODIC_EN) == 0)
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return;
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printk(BIOS_DEBUG, "Periodic SMI.\n");
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}
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void smihandler_southbridge_gpi(
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const struct smm_save_state_ops *save_state_ops)
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{
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struct gpi_status smi_sts;
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gpi_clear_get_smi_status(&smi_sts);
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mainboard_smi_gpi_handler(&smi_sts);
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/* Clear again after mainboard handler */
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gpi_clear_get_smi_status(&smi_sts);
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}
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void smihandler_southbridge_espi(
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const struct smm_save_state_ops *save_state_ops)
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{
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mainboard_smi_espi_handler();
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}
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/* SMI handlers that should be serviced in SCI mode too. */
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static uint32_t smihandler_soc_get_sci_mask(void)
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{
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uint32_t sci_mask =
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SMI_HANDLER_SCI_EN(APM_STS_BIT) |
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SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
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return sci_mask;
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}
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void southbridge_smi_handler(void)
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{
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int i;
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uint32_t smi_sts;
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const struct smm_save_state_ops *save_state_ops;
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/*
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* We need to clear the SMI status registers, or we won't see what's
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* happening in the following calls.
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*/
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smi_sts = pmc_clear_smi_status();
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/*
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* In SCI mode, execute only those SMI handlers that have
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* declared themselves as available for service in that mode
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* using smihandler_soc_get_sci_mask.
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*/
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if (pmc_read_pm1_control() & SCI_EN)
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smi_sts &= smihandler_soc_get_sci_mask();
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if (!smi_sts)
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return;
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save_state_ops = get_smm_save_state_ops();
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/* Call SMI sub handler for each of the status bits */
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for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
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if (!(smi_sts & (1 << i)))
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continue;
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if (southbridge_smi[i] != NULL) {
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|
southbridge_smi[i](save_state_ops);
|
|
} else {
|
|
printk(BIOS_DEBUG,
|
|
"SMI_STS[%d] occurred, but no "
|
|
"handler available.\n", i);
|
|
}
|
|
}
|
|
}
|
|
|
|
static uint32_t em64t100_smm_save_state_get_io_misc_info(void *state)
|
|
{
|
|
em64t100_smm_state_save_area_t *smm_state = state;
|
|
return smm_state->io_misc_info;
|
|
}
|
|
|
|
static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg)
|
|
{
|
|
uintptr_t value = 0;
|
|
em64t100_smm_state_save_area_t *smm_state = state;
|
|
|
|
switch (reg) {
|
|
case RAX:
|
|
value = smm_state->rax;
|
|
break;
|
|
case RBX:
|
|
value = smm_state->rbx;
|
|
break;
|
|
case RCX:
|
|
value = smm_state->rcx;
|
|
break;
|
|
case RDX:
|
|
value = smm_state->rdx;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
return value;
|
|
}
|
|
|
|
static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg,
|
|
uint64_t val)
|
|
{
|
|
em64t100_smm_state_save_area_t *smm_state = state;
|
|
switch (reg) {
|
|
case RAX:
|
|
smm_state->rax = val;
|
|
break;
|
|
case RBX:
|
|
smm_state->rbx = val;
|
|
break;
|
|
case RCX:
|
|
smm_state->rcx = val;
|
|
break;
|
|
case RDX:
|
|
smm_state->rdx = val;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint32_t em64t101_smm_save_state_get_io_misc_info(void *state)
|
|
{
|
|
em64t101_smm_state_save_area_t *smm_state = state;
|
|
return smm_state->io_misc_info;
|
|
}
|
|
|
|
static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg)
|
|
{
|
|
uintptr_t value = 0;
|
|
em64t101_smm_state_save_area_t *smm_state = state;
|
|
|
|
switch (reg) {
|
|
case RAX:
|
|
value = smm_state->rax;
|
|
break;
|
|
case RBX:
|
|
value = smm_state->rbx;
|
|
break;
|
|
case RCX:
|
|
value = smm_state->rcx;
|
|
break;
|
|
case RDX:
|
|
value = smm_state->rdx;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
return value;
|
|
}
|
|
|
|
static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg,
|
|
uint64_t val)
|
|
{
|
|
em64t101_smm_state_save_area_t *smm_state = state;
|
|
switch (reg) {
|
|
case RAX:
|
|
smm_state->rax = val;
|
|
break;
|
|
case RBX:
|
|
smm_state->rbx = val;
|
|
break;
|
|
case RCX:
|
|
smm_state->rcx = val;
|
|
break;
|
|
case RDX:
|
|
smm_state->rdx = val;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
const struct smm_save_state_ops em64t100_smm_ops = {
|
|
.get_io_misc_info = em64t100_smm_save_state_get_io_misc_info,
|
|
.get_reg = em64t100_smm_save_state_get_reg,
|
|
.set_reg = em64t100_smm_save_state_set_reg,
|
|
};
|
|
|
|
const struct smm_save_state_ops em64t101_smm_ops = {
|
|
.get_io_misc_info = em64t101_smm_save_state_get_io_misc_info,
|
|
.get_reg = em64t101_smm_save_state_get_reg,
|
|
.set_reg = em64t101_smm_save_state_set_reg,
|
|
};
|