143 lines
3.1 KiB
C
143 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include "ec.h"
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#include <ec/google/chromeec/ec.h>
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#include <elog.h>
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#include <soc/nvs.h>
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#include <soc/pm.h>
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#include <soc/gpio.h>
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#include "onboard.h"
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/* The wake gpio is SUS_GPIO[0]. */
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#define WAKE_GPIO_EN SUS_GPIO_EN0
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int mainboard_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x99:
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printk(BIOS_DEBUG, "Sample\n");
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gnvs->smif = 0;
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break;
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default:
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return 0;
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}
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/*
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* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*
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* For now, we force the return value to 0 and log all traps to
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* see what's going on.
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*/
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//gnvs->smif = 0;
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return 1;
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}
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static uint8_t mainboard_smi_ec(void)
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{
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uint8_t cmd = google_chromeec_get_event();
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uint16_t pmbase = get_pmbase();
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uint32_t pm1_cnt;
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/* Log this event */
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if (cmd)
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elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
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switch (cmd) {
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case EC_HOST_EVENT_LID_CLOSED:
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printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
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/* Go to S5 */
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pm1_cnt = inl(pmbase + PM1_CNT);
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pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
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outl(pm1_cnt, pmbase + PM1_CNT);
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break;
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}
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return cmd;
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}
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/*
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* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
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* this includes the enable bits in the lower 16 bits.
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*/
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void mainboard_smi_gpi(uint32_t alt_gpio_smi)
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{
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if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
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/* Process all pending events */
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while (mainboard_smi_ec() != 0)
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;
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}
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}
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void mainboard_smi_sleep(uint8_t slp_typ)
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{
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/* Disable USB charging if required */
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switch (slp_typ) {
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case ACPI_S3:
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if (gnvs->s3u0 == 0)
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google_chromeec_set_usb_charge_mode(
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0, USB_CHARGE_MODE_DISABLED);
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if (gnvs->s3u1 == 0)
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google_chromeec_set_usb_charge_mode(
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1, USB_CHARGE_MODE_DISABLED);
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/* Enable wake events */
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google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
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/* Enable wake pin in GPE block. */
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enable_gpe(WAKE_GPIO_EN);
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break;
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case ACPI_S5:
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if (gnvs->s5u0 == 0)
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google_chromeec_set_usb_charge_mode(
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0, USB_CHARGE_MODE_DISABLED);
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if (gnvs->s5u1 == 0)
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google_chromeec_set_usb_charge_mode(
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1, USB_CHARGE_MODE_DISABLED);
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/* Enable wake events */
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google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
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break;
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}
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/* Disable SCI and SMI events */
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google_chromeec_set_smi_mask(0);
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google_chromeec_set_sci_mask(0);
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/* Clear pending events that may trigger immediate wake */
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while (google_chromeec_get_event() != 0)
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;
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/* Set LPC lines to low power in S3/S5. */
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if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
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lpc_set_low_power();
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}
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int mainboard_smi_apmc(uint8_t apmc)
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{
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switch (apmc) {
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case APM_CNT_ACPI_ENABLE:
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google_chromeec_set_smi_mask(0);
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/* Clear all pending events */
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while (google_chromeec_get_event() != 0)
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;
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google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
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break;
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case APM_CNT_ACPI_DISABLE:
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google_chromeec_set_sci_mask(0);
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/* Clear all pending events */
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while (google_chromeec_get_event() != 0)
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;
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google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
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break;
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}
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return 0;
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}
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