109 lines
2.9 KiB
C
109 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <crc_byte.h>
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#include <device/smbus_host.h>
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#include <soc/intel/common/block/smbus/smbuslib.h>
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#include <types.h>
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#include "variants/baseboard/include/eeprom.h"
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#define I2C_ADDR_EEPROM 0x57
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/*
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* Check Signature in EEPROM (M24C32-FMN6TP)
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* If signature is there we assume that that the content is valid
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*/
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int check_signature(const size_t offset, const uint64_t signature)
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{
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u8 blob[8] = {0};
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if (!read_write_config(blob, offset, 0, ARRAY_SIZE(blob))) {
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/* Check signature */
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if (*(uint64_t *)blob == signature) {
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printk(BIOS_DEBUG, "CFG EEPROM: Signature valid.\n");
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return 1;
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}
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printk(BIOS_DEBUG, "CFG EEPROM: Signature invalid - skipping option write.\n");
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return 0;
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}
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return 0;
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}
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/*
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* Read board settings from the EEPROM and verify their checksum.
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* If checksum is valid, we assume the settings are sane as well.
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*/
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static bool get_board_settings_from_eeprom(struct eeprom_board_settings *board_cfg)
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{
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const size_t board_settings_offset = offsetof(struct eeprom_layout, BoardSettings);
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if (read_write_config(board_cfg, board_settings_offset, 0, sizeof(*board_cfg))) {
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printk(BIOS_ERR, "CFG EEPROM: Failed to read board settings\n");
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return false;
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}
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const uint32_t crc =
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CRC(&board_cfg->raw_settings, sizeof(board_cfg->raw_settings), crc32_byte);
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if (crc != board_cfg->signature) {
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printk(BIOS_ERR, "CFG EEPROM: Board settings have invalid checksum\n");
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return false;
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}
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return true;
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}
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struct eeprom_board_settings *get_board_settings(void)
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{
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static struct eeprom_board_settings board_cfg = {0};
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/* Tri-state: -1: settings are invalid, 0: uninitialized, 1: settings are valid */
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static int checked_valid = 0;
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if (checked_valid == 0) {
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const bool success = get_board_settings_from_eeprom(&board_cfg);
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checked_valid = success ? 1 : -1;
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}
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return checked_valid > 0 ? &board_cfg : NULL;
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}
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/* Read data from offset and write it to offset in UPD */
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bool read_write_config(void *blob, size_t read_offset, size_t write_offset, size_t size)
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{
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int ret = 0;
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u32 smb_ctrl_reg = pci_read_config32(PCH_DEV_SMBUS, HOSTC);
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pci_write_config32(PCH_DEV_SMBUS, HOSTC, smb_ctrl_reg | I2C_EN);
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printk(BIOS_SPEW, "%s\tOffset: %04zx\tSize: %02zx\n", __func__,
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read_offset, size);
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/* We can always read two bytes at a time */
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for (size_t i = 0; i < size; i = i + 2) {
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u8 tmp[2] = {0};
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ret = do_smbus_process_call(SMBUS_IO_BASE, I2C_ADDR_EEPROM, 0,
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swab16(read_offset + i), (uint16_t *)&tmp[0]);
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if (ret < 0)
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break;
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/* Write to UPD */
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uint8_t *writePointer = (uint8_t *)blob + write_offset + i;
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if (size > 1 && (size % 2 == 0))
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memcpy(writePointer, tmp, 2);
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else
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*writePointer = tmp[0];
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}
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/* Restore I2C_EN bit */
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pci_write_config32(PCH_DEV_SMBUS, HOSTC, smb_ctrl_reg);
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return ret;
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}
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void report_eeprom_error(const size_t off)
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{
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printk(BIOS_ERR, "MB: Failed to read from EEPROM at addr. 0x%zx\n", off);
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}
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