234 lines
6.7 KiB
C
234 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <bootsplash.h>
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#include <cbfs.h>
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#include <cbmem.h>
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#include <commonlib/fsp.h>
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#include <commonlib/stdlib.h>
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#include <console/console.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <program_loading.h>
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#include <soc/intel/common/vbt.h>
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#include <stage_cache.h>
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#include <string.h>
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#include <timestamp.h>
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#include <types.h>
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#include <mode_switch.h>
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struct fsp_header fsps_hdr;
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struct fsp_multi_phase_get_number_of_phases_params {
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uint32_t number_of_phases;
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uint32_t phases_executed;
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};
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/* Callbacks for SoC/Mainboard specific overrides */
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void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index)
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{
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/* Leave for the SoC/Mainboard to implement if necessary. */
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}
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int __weak soc_fsp_multi_phase_init_is_enable(void)
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{
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return 1;
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}
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/* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2
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* has multiple stages as below.
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*/
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enum fsp_silicon_init_phases {
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FSP_SILICON_INIT_API,
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FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API,
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FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API
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};
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static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint32_t status)
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{
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uint8_t postcode;
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/* Handle any reset request returned by FSP-S APIs */
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fsp_handle_reset(status);
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if (status == FSP_SUCCESS)
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return;
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/* Handle all other errors returned by FSP-S APIs */
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/* Assume video failure if attempted to initialize graphics */
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if (CONFIG(RUN_FSP_GOP) && vbt_get())
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postcode = POST_VIDEO_FAILURE;
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else
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postcode = POST_HW_INIT_FAILURE; /* else generic */
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switch (phases) {
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case FSP_SILICON_INIT_API:
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die_with_post_code(postcode, "FspSiliconInit returned with error 0x%08x\n",
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status);
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break;
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case FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API:
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printk(BIOS_SPEW, "FspMultiPhaseSiInit NumberOfPhases returned 0x%08x\n",
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status);
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break;
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case FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API:
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printk(BIOS_SPEW, "FspMultiPhaseSiInit ExecutePhase returned 0x%08x\n",
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status);
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break;
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default:
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break;
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}
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}
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static void do_silicon_init(struct fsp_header *hdr)
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{
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FSPS_UPD *upd, *supd;
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fsp_silicon_init_fn silicon_init;
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uint32_t status;
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fsp_multi_phase_si_init_fn multi_phase_si_init;
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struct fsp_multi_phase_params multi_phase_params;
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struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
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supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
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fsp_verify_upd_header_signature(supd->FspUpdHeader.Signature, FSPS_UPD_SIGNATURE);
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/* FSPS UPD and coreboot structure sizes should match. However, enforcing the exact
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* match mandates simultaneous updates to coreboot and FSP repos. Allow coreboot
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* to proceed if its UPD structure is smaller than FSP one to enable staggered UPD
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* update process on both sides. The mismatch indicates a temporary build problem,
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* don't leave it like this as FSP default settings can be bad choices for coreboot.
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*/
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if (!hdr->cfg_region_size || hdr->cfg_region_size < sizeof(FSPS_UPD))
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die_with_post_code(POST_INVALID_VENDOR_BINARY,
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"Invalid FSPS UPD region\n");
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else if (hdr->cfg_region_size > sizeof(FSPS_UPD))
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printk(BIOS_ERR, "FSP and coreboot are out of sync! FSPS UPD size > coreboot\n");
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upd = xmalloc(hdr->cfg_region_size);
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memcpy(upd, supd, hdr->cfg_region_size);
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/* Give SoC/mainboard a chance to populate entries */
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platform_fsp_silicon_init_params_cb(upd);
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/* Populate logo related entries */
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if (CONFIG(BMP_LOGO))
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soc_load_logo(upd);
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/* Call SiliconInit */
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silicon_init = (void *) (uintptr_t)(hdr->image_base +
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hdr->silicon_init_entry_offset);
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fsp_debug_before_silicon_init(silicon_init, supd, upd);
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timestamp_add_now(TS_FSP_SILICON_INIT_START);
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post_code(POST_FSP_SILICON_INIT);
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if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
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status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd);
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else
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status = silicon_init(upd);
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printk(BIOS_ERR, "FSPS returned %x\n", status);
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timestamp_add_now(TS_FSP_SILICON_INIT_END);
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post_code(POST_FSP_SILICON_EXIT);
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if (CONFIG(BMP_LOGO))
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bmp_release_logo();
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fsp_debug_after_silicon_init(status);
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fsps_return_value_handler(FSP_SILICON_INIT_API, status);
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/* Reinitialize CPUs if FSP-S has done MP Init */
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if (CONFIG(USE_INTEL_FSP_MP_INIT))
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do_mpinit_after_fsp();
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if (!CONFIG(PLATFORM_USES_FSP2_2))
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return;
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/* Check if SoC user would like to call Multi Phase Init */
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if (!soc_fsp_multi_phase_init_is_enable())
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return;
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/* Call MultiPhaseSiInit */
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multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base +
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hdr->multi_phase_si_init_entry_offset);
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/* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */
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if (multi_phase_si_init == NULL)
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return;
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post_code(POST_FSP_MULTI_PHASE_SI_INIT_ENTRY);
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timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_START);
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/* Get NumberOfPhases Value */
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multi_phase_params.multi_phase_action = GET_NUMBER_OF_PHASES;
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multi_phase_params.phase_index = 0;
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multi_phase_params.multi_phase_param_ptr = &multi_phase_get_number;
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status = multi_phase_si_init(&multi_phase_params);
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fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API, status);
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/* Execute Multi Phase Execution */
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for (int i = 1; i <= multi_phase_get_number.number_of_phases; i++) {
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printk(BIOS_SPEW, "Executing Phase %d of FspMultiPhaseSiInit\n", i);
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/*
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* Give SoC/mainboard a chance to perform any operation before
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* Multi Phase Execution
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*/
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platform_fsp_multi_phase_init_cb(i);
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multi_phase_params.multi_phase_action = EXECUTE_PHASE;
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multi_phase_params.phase_index = i;
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multi_phase_params.multi_phase_param_ptr = NULL;
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status = multi_phase_si_init(&multi_phase_params);
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fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API, status);
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}
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timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END);
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post_code(POST_FSP_MULTI_PHASE_SI_INIT_EXIT);
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}
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static int fsps_get_dest(const struct fsp_load_descriptor *fspld, void **dest,
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size_t size, const struct region_device *source)
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{
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*dest = cbmem_add(CBMEM_ID_REFCODE, size);
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if (*dest == NULL)
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return -1;
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return 0;
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}
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void fsps_load(void)
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{
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struct fsp_load_descriptor fspld = {
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.fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_S_CBFS),
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.get_destination = fsps_get_dest,
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};
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struct prog *fsps = &fspld.fsp_prog;
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static int load_done;
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if (load_done)
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return;
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if (resume_from_stage_cache()) {
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printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n");
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stage_cache_load_stage(STAGE_REFCODE, fsps);
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if (fsp_validate_component(&fsps_hdr, prog_rdev(fsps)) != CB_SUCCESS)
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die("On resume fsps header is invalid\n");
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load_done = 1;
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return;
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}
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if (fsp_load_component(&fspld, &fsps_hdr) != CB_SUCCESS)
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die("FSP-S failed to load\n");
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stage_cache_add(STAGE_REFCODE, fsps);
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load_done = 1;
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}
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void fsp_silicon_init(void)
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{
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fsps_load();
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do_silicon_init(&fsps_hdr);
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}
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__weak void soc_load_logo(FSPS_UPD *supd) { }
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