57 lines
1.6 KiB
Plaintext
57 lines
1.6 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <memlayout.h>
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#include <arch/header.ld>
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/* SYSTEM_IMEM : 0x14680000 - 0x146AB000 */
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#define SSRAM_START(addr) REGION_START(ssram, addr)
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#define SSRAM_END(addr) REGION_END(ssram, addr)
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/* BOOT_IMEM : 0x14800000 - 0x14980000 */
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#define BSRAM_START(addr) REGION_START(bsram, addr)
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#define BSRAM_END(addr) REGION_END(bsram, addr)
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/* AOP : 0x0B000000 - 0x0B100000 */
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#define AOPSRAM_START(addr) REGION_START(aopsram, addr)
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#define AOPSRAM_END(addr) REGION_END(aopsram, addr)
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SECTIONS
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{
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AOPSRAM_START(0x0B000000)
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REGION(aop, 0x0B000000, 0x100000, 4096)
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AOPSRAM_END(0x0B100000)
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SSRAM_START(0x14680000)
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OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K)
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REGION(qcsdi, 0x14699000, 52K, 4K)
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SSRAM_END(0x146AB000)
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BSRAM_START(0x14800000)
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REGION(pbl_timestamps, 0x14800000, 84K, 4K)
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BOOTBLOCK(0x14819000, 40K)
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PRERAM_CBFS_CACHE(0x14823000, 70K)
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PRERAM_CBMEM_CONSOLE(0x14834800, 32K)
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TIMESTAMP(0x1483C800, 1K)
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TTB(0x1483D000, 56K)
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STACK(0x1484B000, 16K)
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VBOOT2_WORK(0x1484F000, 12K)
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DMA_COHERENT(0x14853000, 8K)
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REGION(ddr_training, 0x14855000, 8K, 4K)
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REGION(qclib_serial_log, 0x14857000, 4K, 4K)
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REGION(ddr_information, 0x1485B000, 1K, 1K)
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FMAP_CACHE(0x1485B400, 2K)
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CBFS_MCACHE(0x1485BC00,8K)
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REGION(dcb, 0x14875000, 32K, 4K)
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REGION(pmic, 0x1487D000, 96K, 4K)
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REGION(qclib, 0x14895000, 748K, 4K)
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BSRAM_END(0x14950000)
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DRAM_START(0x80000000)
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/* Various hardware/software subsystems make use of this area */
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REGION(dram_aop, 0x80800000, 0x040000, 0x1000)
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REGION(dram_soc, 0x80900000, 0x200000, 0x1000)
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BL31(0x80B00000, 1M)
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POSTRAM_CBFS_CACHE(0x9F800000, 16M)
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RAMSTAGE(0xA0800000, 16M)
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}
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