122 lines
2.8 KiB
C
122 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/bootblock.h>
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#include <device/pci_ops.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/rcba.h>
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#include <soc/spi.h>
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#include <soc/pm.h>
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#include <soc/romstage.h>
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#include <southbridge/intel/common/early_spi.h>
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static void map_rcba(void)
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{
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pci_write_config32(PCH_DEV_LPC, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
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}
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static void enable_port80_on_lpc(void)
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{
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/* Enable port 80 POST on LPC. The chipset does this by default,
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* but it doesn't appear to hurt anything. */
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u32 gcs = RCBA32(GCS);
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gcs = gcs & ~0x4;
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RCBA32(GCS) = gcs;
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}
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static void set_spi_speed(void)
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{
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u32 fdod;
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u8 ssfc;
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/* Observe SPI Descriptor Component Section 0 */
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SPIBAR32(SPIBAR_FDOC) = 0x1000;
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/* Extract the Write/Erase SPI Frequency from descriptor */
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fdod = SPIBAR32(SPIBAR_FDOD);
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fdod >>= 24;
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fdod &= 7;
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/* Set Software Sequence frequency to match */
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ssfc = SPIBAR8(SPIBAR_SSFC + 2);
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ssfc &= ~7;
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ssfc |= fdod;
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SPIBAR8(SPIBAR_SSFC + 2) = ssfc;
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}
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static void pch_enable_bars(void)
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{
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/* Set up southbridge BARs */
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pci_write_config32(PCH_DEV_LPC, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
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pci_write_config32(PCH_DEV_LPC, PMBASE, ACPI_BASE_ADDRESS | 1);
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pci_write_config8(PCH_DEV_LPC, ACPI_CNTL, ACPI_EN);
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pci_write_config32(PCH_DEV_LPC, GPIO_BASE, GPIO_BASE_ADDRESS | 1);
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/* Enable GPIO functionality. */
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pci_write_config8(PCH_DEV_LPC, GPIO_CNTL, GPIO_EN);
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}
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static void pch_early_lpc(void)
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{
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pch_enable_bars();
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/* Set COM1/COM2 decode range */
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pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, 0x0010);
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/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */
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u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
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COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
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pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_config);
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/* Enable IOAPIC */
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RCBA16(OIC) = 0x0100;
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/* Read back for posted write */
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(void)RCBA16(OIC);
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/* Set HPET address and enable it */
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RCBA32_AND_OR(HPTC, ~3, 1 << 7);
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/*
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* Reading the register back guarantees that the write is
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* done before we use the configured base address below.
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*/
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(void)RCBA32(HPTC);
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/* Enable HPET to start counter */
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setbits32((void *)HPET_BASE_ADDRESS + 0x10, 1 << 0);
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/* Disable reset */
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RCBA32_OR(GCS, 1 << 5);
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/* TCO timer halt */
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u16 reg16 = inb(ACPI_BASE_ADDRESS + TCO1_CNT);
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reg16 |= TCO_TMR_HLT;
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outb(reg16, ACPI_BASE_ADDRESS + TCO1_CNT);
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/* Enable upper 128 bytes of CMOS */
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RCBA32_OR(RC, 1 << 2);
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/* Disable unused device (always) */
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RCBA32_OR(FD, PCH_DISABLE_ALWAYS);
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}
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/* Defined in Lynx Point code */
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void uart_bootblock_init(void);
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void bootblock_early_southbridge_init(void)
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{
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map_rcba();
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enable_spi_prefetching_and_caching();
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enable_port80_on_lpc();
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set_spi_speed();
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pch_early_lpc();
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if (CONFIG(SERIALIO_UART_CONSOLE))
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uart_bootblock_init();
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}
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