240 lines
6.5 KiB
C
240 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <assert.h>
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#include <cpu/intel/turbo.h>
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#include <device/mmio.h>
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#include <device/pci.h>
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#include <intelblocks/acpi.h>
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#include <intelblocks/cpulib.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/soc_util.h>
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#include <soc/util.h>
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int soc_madt_sci_irq_polarity(int sci)
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{
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if (sci >= 20)
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return MP_IRQ_POLARITY_LOW;
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else
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return MP_IRQ_POLARITY_HIGH;
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}
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uint32_t soc_read_sci_irq_select(void)
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{
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struct device *dev = PCH_DEV_PMC;
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if (!dev)
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return 0;
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return pci_read_config32(dev, PMC_ACPI_CNT);
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}
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void soc_fill_fadt(acpi_fadt_t *fadt)
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{
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/* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */
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fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE);
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}
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void uncore_inject_dsdt(const struct device *device)
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{
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struct iiostack_resource stack_info = {0};
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/* Only add RTxx entries once. */
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if (device->bus->secondary != 0)
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return;
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get_iiostack_info(&stack_info);
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acpigen_write_scope("\\_SB");
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for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) {
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const STACK_RES *ri = &stack_info.res[stack];
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char rtname[16];
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snprintf(rtname, sizeof(rtname), "RT%02x", stack);
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acpigen_write_name(rtname);
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printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n",
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rtname, stack);
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acpigen_write_resourcetemplate_header();
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/* bus resource */
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acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit,
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0x0, (ri->BusLimit - ri->BusBase + 1));
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/* additional io resources on socket 0 bus 0 */
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if (stack == 0) {
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/* ACPI 6.4.2.5 I/O Port Descriptor */
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acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1);
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/* IO decode CF8-CFF */
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
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}
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/* IO resource */
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acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase,
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ri->PciResourceIoLimit, 0x0,
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(ri->PciResourceIoLimit - ri->PciResourceIoBase + 1));
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/* additional mem32 resources on socket 0 bus 0 */
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if (stack == 0) {
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acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS,
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(VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0,
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VGA_BASE_SIZE);
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acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
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(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
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SPI_BASE_SIZE);
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}
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/* Mem32 resource */
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acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
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ri->PciResourceMem32Limit, 0x0,
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(ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1));
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/* Mem64 resource */
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acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base,
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ri->PciResourceMem64Limit, 0x0,
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(ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
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acpigen_write_resourcetemplate_footer();
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}
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acpigen_pop_len();
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}
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/* TODO: See if we can use the common generate_p_state_entries */
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void soc_power_states_generation(int core, int cores_per_package)
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{
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int ratio_min, ratio_max, ratio_turbo, ratio_step;
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int coord_type, power_max, power_unit, num_entries;
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int ratio, power, clock, clock_max;
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msr_t msr;
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/* Determine P-state coordination type from MISC_PWR_MGMT[0] */
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msr = rdmsr(MSR_MISC_PWR_MGMT);
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if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
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coord_type = SW_ANY;
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else
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coord_type = HW_ALL;
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/* Get bus ratio limits and calculate clock speeds */
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msr = rdmsr(MSR_PLATFORM_INFO);
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ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
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/* Determine if this CPU has configurable TDP */
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if (cpu_config_tdp_levels()) {
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/* Set max ratio to nominal TDP ratio */
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msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
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ratio_max = msr.lo & 0xff;
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} else {
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/* Max Non-Turbo Ratio */
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ratio_max = (msr.lo >> 8) & 0xff;
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}
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clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ;
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/* Calculate CPU TDP in mW */
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msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
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power_unit = 2 << ((msr.lo & 0xf) - 1);
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msr = rdmsr(MSR_PKG_POWER_SKU);
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power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
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/* Write _PCT indicating use of FFixedHW */
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acpigen_write_empty_PCT();
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/* Write _PPC with no limit on supported P-state */
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acpigen_write_PPC_NVS();
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/* Write PSD indicating configured coordination type */
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acpigen_write_PSD_package(core, 1, coord_type);
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/* Add P-state entries in _PSS table */
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acpigen_write_name("_PSS");
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/* Determine ratio points */
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ratio_step = PSS_RATIO_STEP;
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num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
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if (num_entries > PSS_MAX_ENTRIES) {
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ratio_step += 1;
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num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
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}
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/* P[T] is Turbo state if enabled */
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if (get_turbo_state() == TURBO_ENABLED) {
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/* _PSS package count including Turbo */
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acpigen_write_package(num_entries + 2);
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msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
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ratio_turbo = msr.lo & 0xff;
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/* Add entry for Turbo ratio */
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acpigen_write_PSS_package(
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clock_max + 1, /* MHz */
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power_max, /* mW */
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PSS_LATENCY_TRANSITION, /* lat1 */
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PSS_LATENCY_BUSMASTER, /* lat2 */
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ratio_turbo << 8, /* control */
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ratio_turbo << 8); /* status */
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} else {
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/* _PSS package count without Turbo */
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acpigen_write_package(num_entries + 1);
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}
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/* First regular entry is max non-turbo ratio */
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acpigen_write_PSS_package(
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clock_max, /* MHz */
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power_max, /* mW */
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PSS_LATENCY_TRANSITION, /* lat1 */
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PSS_LATENCY_BUSMASTER, /* lat2 */
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ratio_max << 8, /* control */
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ratio_max << 8); /* status */
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/* Generate the remaining entries */
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for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
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ratio >= ratio_min; ratio -= ratio_step) {
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/* Calculate power at this ratio */
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power = common_calculate_power_ratio(power_max, ratio_max, ratio);
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clock = ratio * CONFIG_CPU_BCLK_MHZ;
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//clock = 1;
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acpigen_write_PSS_package(
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clock, /* MHz */
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power, /* mW */
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PSS_LATENCY_TRANSITION, /* lat1 */
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PSS_LATENCY_BUSMASTER, /* lat2 */
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ratio << 8, /* control */
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ratio << 8); /* status */
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}
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/* Fix package length */
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acpigen_pop_len();
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}
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unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current)
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{
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struct device *cpu;
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uint8_t num_cpus = 0;
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for (cpu = all_devices; cpu; cpu = cpu->next) {
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if ((cpu->path.type != DEVICE_PATH_APIC) ||
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(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
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continue;
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}
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if (!cpu->enabled)
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continue;
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
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num_cpus, cpu->path.apic.apic_id);
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num_cpus++;
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}
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return current;
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}
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