177 lines
5.1 KiB
Plaintext
177 lines
5.1 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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config PLATFORM_USES_FSP2_0
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bool
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default n
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help
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Include FSP 2.0 wrappers and functionality
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config PLATFORM_USES_FSP2_1
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bool
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default n
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select PLATFORM_USES_FSP2_0
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select FSP_USES_CB_STACK
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select FSP_PEIM_TO_PEIM_INTERFACE
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help
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Include FSP 2.1 wrappers and functionality.
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Features added into FSP 2.1 specification that impacts coreboot are:
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1. Remove FSP stack switch and use the same stack with boot firmware
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2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE
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if PLATFORM_USES_FSP2_0
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config FSP_USE_REPO
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bool "Use binaries of the Intel FSP repository on GitHub"
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depends on HAVE_INTEL_FSP_REPO
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default y
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help
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When selecting this option, the SoC must set FSP_HEADER_PATH
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and FSP_FD_PATH correctly so FSP splitting works.
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config ADD_FSP_BINARIES
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bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO
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default y if FSP_USE_REPO
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help
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Add the FSP-M and FSP-S binaries to CBFS.
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config FSP_T_CBFS
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string "Name of FSP-T in CBFS"
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depends on FSP_CAR
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default "fspt.bin"
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config FSP_S_CBFS
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string "Name of FSP-S in CBFS"
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default "fsps.bin"
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config FSP_M_CBFS
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string "Name of FSP-M in CBFS"
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default "fspm.bin"
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config FSP_T_FILE
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string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_USE_REPO
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depends on ADD_FSP_BINARIES
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depends on FSP_CAR
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default "$(obj)/Fsp_T.fd" if FSP_USE_REPO
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help
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The path and filename of the Intel FSP-T binary for this platform.
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config FSP_M_FILE
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string "Intel FSP-M (memory init) binary path and filename" if !FSP_USE_REPO
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depends on ADD_FSP_BINARIES
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default "$(obj)/Fsp_M.fd" if FSP_USE_REPO
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help
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The path and filename of the Intel FSP-M binary for this platform.
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config FSP_S_FILE
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string "Intel FSP-S (silicon init) binary path and filename" if !FSP_USE_REPO
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depends on ADD_FSP_BINARIES
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default "$(obj)/Fsp_S.fd" if FSP_USE_REPO
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help
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The path and filename of the Intel FSP-S binary for this platform.
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config FSP_CAR
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bool
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default n
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help
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Use FSP APIs to initialize & Tear Down the Cache-As-Ram
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config FSP_M_XIP
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bool
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default n
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help
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Select this value when FSP-M is execute-in-place.
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config FSP_T_XIP
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bool
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default n
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help
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Select this value when FSP-T is execute-in-place.
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config FSP_USES_CB_STACK
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bool
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default n
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help
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Enable support for fsp to use same stack as coreboot.
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This option allows fsp to continue using coreboot stack
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without reinitializing stack pointer. This feature is
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supported Icelake onwards.
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config FSP_TEMP_RAM_SIZE
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hex
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depends on FSP_USES_CB_STACK
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help
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The amount of anticipated heap usage in CAR by FSP to setup HOB.
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This configuration is applicable for FSP specification using shared
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stack with coreboot/bootloader.
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Sync this value with Platform FSP integration guide recommendation.
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config FSP2_0_USES_TPM_MRC_HASH
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bool
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depends on TPM1 || TPM2
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depends on VBOOT && VBOOT_STARTS_IN_BOOTBLOCK
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default y if HAS_RECOVERY_MRC_CACHE
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default n
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select VBOOT_HAS_REC_HASH_SPACE
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help
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Store hash of trained recovery MRC cache in NVRAM space in TPM.
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Use the hash to validate recovery MRC cache before using it.
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This hash needs to be updated every time recovery mode training
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is recomputed, or if the hash does not match recovery MRC cache.
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Selecting this option requires that TPM already be setup by this
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point in time. Thus it is only compatible when the option
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VBOOT_STARTS_IN_BOOTBLOCK is selected, which causes verstage and
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TPM setup to occur prior to memory initialization.
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config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
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bool
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help
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This is selected by SoC or mainboard to supply their own
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concept of a version for the memory settings respectively.
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This allows deployed systems to bump their version number
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with the same FSP which will trigger a retrain of the memory.
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config FSP_PEIM_TO_PEIM_INTERFACE
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bool
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select FSP_USES_MP_SERVICES_PPI
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help
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This option allows SOC user to create specific PPI for Intel FSP
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usage, coreboot will provide required PPI structure definitions
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along with all APIs as per EFI specification. So far this feature
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is limited till EFI_PEI_MP_SERVICE_PPI and this option might be
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useful to add further PPI if required.
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config HAVE_FSP_LOGO_SUPPORT
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bool
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default n
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config FSP2_0_DISPLAY_LOGO
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bool "Enable logo"
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default n
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depends on HAVE_FSP_LOGO_SUPPORT
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help
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Uses the FSP to display the boot logo. This method supports a
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BMP file only. The uncompressed size can be up to 1 MB. The logo can be compressed
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using LZMA.
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config FSP2_0_LOGO_FILE_NAME
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string "Logo file"
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depends on FSP2_0_DISPLAY_LOGO
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp"
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if FSP_PEIM_TO_PEIM_INTERFACE
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source "src/drivers/intel/fsp2_0/ppi/Kconfig"
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endif
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endif
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