263 lines
7.1 KiB
C
263 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <console/usb.h>
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#include <string.h>
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#include <cbmem.h>
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#include <cbfs.h>
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#include <cf9_reset.h>
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#include <ip_checksum.h>
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#include <memory_info.h>
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#include <mrc_cache.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/dram/ddr3.h>
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#include <smbios.h>
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#include <spd.h>
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#include <security/vboot/vboot_common.h>
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#include <commonlib/region.h>
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#include <types.h>
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#include "raminit.h"
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#include "pei_data.h"
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#include "haswell.h"
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#define MRC_CACHE_VERSION 1
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void save_mrc_data(struct pei_data *pei_data)
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{
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/* Save the MRC S3 restore data to cbmem */
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mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output,
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pei_data->mrc_output_len);
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}
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static void prepare_mrc_cache(struct pei_data *pei_data)
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{
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size_t mrc_size;
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/* Preset just in case there is an error */
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pei_data->mrc_input = NULL;
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pei_data->mrc_input_len = 0;
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pei_data->mrc_input =
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mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
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MRC_CACHE_VERSION,
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&mrc_size);
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if (!pei_data->mrc_input)
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/* Error message printed in find_current_mrc_cache */
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return;
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pei_data->mrc_input_len = mrc_size;
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printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__,
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pei_data->mrc_input, mrc_size);
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}
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static const char *const ecc_decoder[] = {
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"inactive",
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"active on IO",
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"disabled on IO",
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"active",
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};
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/* Print out the memory controller configuration, as per the values in its registers. */
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static void report_memory_config(void)
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{
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int i;
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const u32 addr_decoder_common = MCHBAR32(MAD_CHNL);
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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(MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
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printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
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(addr_decoder_common >> 0) & 3,
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < NUM_CHANNELS; i++) {
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const u32 ch_conf = MCHBAR32(MAD_DIMM(i));
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printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
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printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
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printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
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((ch_conf >> 22) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " rank interleave %s\n",
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((ch_conf >> 21) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n",
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
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((ch_conf >> 17) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? "" : ", selected");
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printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 20) & 1) ? "x16" : "x8 or x32",
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((ch_conf >> 18) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? ", selected" : "");
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}
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}
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/**
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* Find PEI executable in coreboot filesystem and execute it.
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*
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* @param pei_data: configuration data for UEFI PEI reference code
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*/
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void sdram_initialize(struct pei_data *pei_data)
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{
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int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1)));
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printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
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/*
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* Always pass in mrc_cache data. The driver will determine
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* whether to use the data or not.
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*/
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prepare_mrc_cache(pei_data);
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/* If MRC data is not found, we cannot continue S3 resume */
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if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
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post_code(POST_RESUME_FAILURE);
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printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__);
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system_reset();
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}
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/* Pass console handler in pei_data */
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pei_data->tx_byte = do_putchar;
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/*
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* Locate and call UEFI System Agent binary. The binary needs to be at a fixed offset
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* in the flash and can therefore only reside in the COREBOOT fmap region. We don't care
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* about leaking the mapping.
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*/
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entry = cbfs_ro_map("mrc.bin", NULL);
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if (entry) {
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int rv = entry(pei_data);
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/* The mrc.bin reconfigures USB, so usbdebug needs to be reinitialized */
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if (CONFIG(USBDEBUG_IN_PRE_RAM))
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usbdebug_hw_init(true);
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if (rv) {
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switch (rv) {
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case -1:
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printk(BIOS_ERR, "PEI version mismatch.\n");
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break;
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case -2:
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printk(BIOS_ERR, "Invalid memory frequency.\n");
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break;
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default:
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printk(BIOS_ERR, "MRC returned %x.\n", rv);
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}
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die_with_post_code(POST_INVALID_VENDOR_BINARY,
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"Nonzero MRC return value.\n");
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}
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} else {
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die("UEFI PEI System Agent not found.\n");
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}
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/* Print the MRC version after executing the UEFI PEI stage */
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u32 version = MCHBAR32(MRC_REVISION);
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printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n",
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(version >> 24) & 0xff, (version >> 16) & 0xff,
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(version >> 8) & 0xff, (version >> 0) & 0xff);
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report_memory_config();
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}
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static bool nb_supports_ecc(const uint32_t capid0_a)
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{
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return !(capid0_a & CAPID_ECCDIS);
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}
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static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
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{
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return !(capid0_a & CAPID_DDPCD) + 1;
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}
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static uint16_t nb_number_of_channels(const uint32_t capid0_a)
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{
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return !(capid0_a & CAPID_PDCD) + 1;
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}
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static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a)
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{
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uint32_t ddrsz;
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/* Values from documentation, which assume two DIMMs per channel */
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switch (CAPID_DDRSZ(capid0_a)) {
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case 1:
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ddrsz = 8192;
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break;
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case 2:
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ddrsz = 2048;
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break;
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case 3:
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ddrsz = 512;
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break;
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default:
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ddrsz = 16384;
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break;
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}
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/* Account for the maximum number of DIMMs per channel */
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return (ddrsz / 2) * nb_slots_per_channel(capid0_a);
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}
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void setup_sdram_meminfo(struct pei_data *pei_data)
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{
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struct memory_info *mem_info;
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struct dimm_info *dimm;
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int ch, d_num;
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int dimm_cnt = 0;
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mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
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if (!mem_info)
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die("Failed to add memory info to CBMEM.\n");
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memset(mem_info, 0, sizeof(struct memory_info));
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const u32 ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
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for (ch = 0; ch < NUM_CHANNELS; ch++) {
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const u32 ch_conf = MCHBAR32(MAD_DIMM(ch));
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/* DIMMs A/B */
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for (d_num = 0; d_num < NUM_SLOTS; d_num++) {
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const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256;
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if (dimm_size) {
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dimm = &mem_info->dimm[dimm_cnt];
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dimm->dimm_size = dimm_size;
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dimm->ddr_type = MEMORY_TYPE_DDR3;
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dimm->ddr_frequency = ddr_frequency;
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dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1);
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dimm->channel_num = ch;
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dimm->dimm_num = d_num;
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dimm->bank_locator = ch * 2;
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memcpy(dimm->serial,
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&pei_data->spd_data[dimm_cnt][SPD_DIMM_SERIAL_NUM],
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SPD_DIMM_SERIAL_LEN);
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memcpy(dimm->module_part_number,
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&pei_data->spd_data[dimm_cnt][SPD_DIMM_PART_NUM],
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SPD_DIMM_PART_LEN);
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dimm->mod_id =
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(pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID2] << 8) |
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(pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xff);
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dimm->mod_type = SPD_SODIMM;
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dimm->bus_width = MEMORY_BUS_WIDTH_64;
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dimm_cnt++;
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}
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}
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}
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mem_info->dimm_cnt = dimm_cnt;
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const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
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const uint16_t channels = nb_number_of_channels(capid0_a);
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mem_info->ecc_capable = nb_supports_ecc(capid0_a);
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mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
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mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a);
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}
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