133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <arch/romstage.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <cbmem.h>
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#include <program_loading.h>
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#include <cpu/intel/smm_reloc.h>
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#include <types.h>
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#include "gm45.h"
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/*
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* Decodes used Graphics Mode Select (GMS) to kilobytes.
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* The options for 1M, 4M, 8M and 16M preallocated igd memory are
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* undocumented but are verified to work.
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*/
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u32 decode_igd_memory_size(const u32 gms)
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{
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static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256,
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96, 160, 224, 352 };
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if (gms >= ARRAY_SIZE(ggc2uma))
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die("Bad Graphics Mode Select (GMS) setting.\n");
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return ggc2uma[gms] << 10;
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}
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/** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */
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u32 decode_igd_gtt_size(const u32 gsm)
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{
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switch (gsm) {
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case 0:
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return 0 << 10;
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case 1:
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return 1 << 10;
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case 3:
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case 9:
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return 2 << 10;
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case 10:
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return 3 << 10;
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case 11:
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return 4 << 10;
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default:
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die("Bad Graphics Stolen Memory (GSM) setting.\n");
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return 0;
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}
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}
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/* Decodes TSEG region size to kilobytes. */
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u32 decode_tseg_size(u8 esmramc)
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{
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if (!(esmramc & 1))
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return 0;
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switch ((esmramc >> 1) & 3) {
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case 0:
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return 1 << 10;
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case 1:
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return 2 << 10;
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case 2:
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return 8 << 10;
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case 3:
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default:
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die("Bad TSEG setting.\n");
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}
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}
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static uintptr_t northbridge_get_tseg_base(void)
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{
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const pci_devfn_t dev = PCI_DEV(0, 0, 0);
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u32 tor;
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/* Top of Lower Usable DRAM */
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tor = (pci_read_config16(dev, D0F0_TOLUD) & 0xfff0) << 16;
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/* Graphics memory comes next */
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const u32 ggc = pci_read_config16(dev, D0F0_GGC);
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const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);
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if (!(ggc & 2)) {
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/* Graphics memory */
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tor -= decode_igd_memory_size((ggc >> 4) & 0xf) << 10;
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/* GTT Graphics Stolen Memory Size (GGMS) */
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tor -= decode_igd_gtt_size((ggc >> 8) & 0xf) << 10;
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}
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/* TSEG size */
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tor -= decode_tseg_size(esmramc) << 10;
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return tor;
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}
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static size_t northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
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return decode_tseg_size(esmramc) << 10;
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}
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/* Depending of UMA and TSEG configuration, TSEG might start at any
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* 1 MiB alignment. As this may cause very greedy MTRR setup, push
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* CBMEM top downwards to 4 MiB boundary.
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*/
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void *cbmem_top_chipset(void)
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{
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uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
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return (void *) top_of_ram;
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
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* RAM to cover both cbmem as the TSEG region.
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*/
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
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northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
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}
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