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6 Commits

Author SHA1 Message Date
Martin Roth d57ace259a AUTHORS: Move src/cpu copyrights into AUTHORS file 
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id6070fb586896653a1e44951a6af8f42f93b5a7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2019-09-10 12:51:22 +00:00
Elyes HAOUAS 419bfbc1f1 src: Move common IA-32 MSRs to <cpu/x86/msr.h> 
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.

Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-10-11 21:06:53 +00:00
Elyes HAOUAS 4f4151abdb src/cpu/via/nano: Remove unneeded include 
Change-Id: I656b11add77012271ccc0c80dfcf97d20937dba2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2018-09-25 14:12:56 +00:00
Patrick Georgi a73b93157f tree: drop last paragraph of GPL copyright header 
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
 2015-10-31 21:37:39 +01:00
Martin Roth 4c3ab7376e cpu: Fix spelling 
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2013-07-11 22:36:59 +02:00
Alexandru Gagniuc e644bada02 VIA Nano: Add support for VIA Nano CPUs 
Add code to do the following for the VIA Nano CPUs
- Update microcode
- Set maximum frequency
- Initialize power states
- Set up cache

Attempting to change the voltage or frequency of the CPU without
applying the microcode update will hang the CPU, so we only do
transitions if we can verify the microcode has been updated.

The microcode is updated directly from CBFS. No microcode is
included in ramstage. The microcode is not included in this
commit.

To get the microcode, run bios_extract on the manufacturer supplied
BIOS, and look for the file marked "P6 Microcode". Include this
file in CBFS.
You can have the build system include this file automatically by
selecting Expert Mode, then look under
'Chipset' -> 'Include CPU microcode in CBFS' ->
Include external microcode file (check)
'Path and filename of CPU microcode' should contain the location of
the microcode file previously extracted.

Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1257
Tested-by: build bot (Jenkins)
 2012-09-05 03:43:02 +02:00