Commit Graph

30317 Commits

Author SHA1 Message Date
Martin Roth 4e09ebeded Add .editorconfig file
.editorconfig files are widely supported and offer basic configuration
 options for the project.

This sets the indention style, line-ending, character set,  tells the
editor to make sure there's a newline at the end of the file and to
strip trailing whitespace.

For directories within the coreboot directory that would prefer a
different setting, additional  .editorconfig files can be placed in
those directories to override any of these settings.

See the EditorConfig website for more information.
https://web.archive.org/web/https://editorconfig.org

Change-Id: Iecf1c5450edb0db533569189aa45233b91997870
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-10 12:52:18 +00:00
Martin Roth d57ace259a AUTHORS: Move src/cpu copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id6070fb586896653a1e44951a6af8f42f93b5a7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-10 12:51:22 +00:00
Martin Roth 838d8b07ab AUTHORS: Move src/cpu/intel copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I39f52764dc377c25953ef5dba16982a0b4637cdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-10 12:51:10 +00:00
Martin Roth 97ea346fdf AUTHORS: Move src/cpu/amd copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I77275adb7c15b242e319805b8a60b7755fa25db5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-10 12:50:59 +00:00
Martin Roth 65244a7f66 AUTHORS: Move src/console copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I2f350cc3008b17516b5a42cdf07e28d2da5995e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-10 12:50:44 +00:00
Martin Roth 0443ac2827 AUTHORS: Move src/commonlib copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4c9351652d81040cc4e7b85bdd1ba85709a74192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-10 12:50:35 +00:00
Martin Roth 20bbd81201 AUTHORS: Move src/arch/x86 copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ifd4329905847d9dd06de67b9a443c8ee50c0e7a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-10 12:50:17 +00:00
Nick Vaccaro 98189771ab mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO..

 - change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as
   EC_PCH_ARCORE_INT_L is active low

 - add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge

BUG=b:139384979
BRANCH=none
TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage",
flash & boot nocturne in dev mode, verify that volume up and down
buttons work in the dev screen and that the device boots properly into
the kernel.

Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-10 12:17:56 +00:00
Frank_Chu 687c419cde mb/google/hatch/variants/helios: Modify FPU power on sequence
pull in the FPU VDDIO turn on to fix the power leakage problem
on FPU VDDIO and FPU CS during power on sequence.

BUG=b:138638571
BRANCH=none
TEST=emerge-hatch coreboot chromeos-bootimage

Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I3f6bf3676922e987c2e282b697a2333e2d90289e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-10 12:12:56 +00:00
Wisley Chen 188f64172b mb/google/octopus: Add a new sku for meep
Add a new sku4 for meep:
sku4: Stylus + no rear camera

BUG=b:140360096
TEST=emerge-octopus coreboot

Change-Id: Icde7f032c0acf7562b5d5f2c6a8b0c2de91c45b2
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-09-10 12:11:39 +00:00
Peichao Wang 632283092c mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock
Tune I2C bus 1, 2 and 3 clock and make them meet spec.

BUG=b:140665478
TEST==flash coreboot to the DUT and measure I2C bus 1,2,3 clock
frequency less than 400KHz

Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6b2a51a866e57d13fe528452e4efdcf17a72317f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35298
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10 12:11:30 +00:00
Patrick Rudolph 203061c24a soc/intel/skylake: Add option to toggle Hyper-Threading
Tested on Supermicro X11SSH-TF.

Change-Id: I3ebab68ff868c78105bb4b35abffb92f3ccf1705
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-10 10:57:23 +00:00
Peichao Wang 0328a723b8 mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD respectively
1. SKU1 for eMMC
2. SKU2 for SSD

BUG=b:140008849, b:140573677
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35204
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09 23:45:33 +00:00
Marshall Dawson 80d0b01b38 soc/amd/picasso: Update TSC and monotonic timer
Picasso's TimeStamp Counter is a new design and different than
Stoney Ridge.  Although advertised as invariant, the ST TSC did
not become so until midway through POST making it an unreliable
source for measuring time.  This is not the case for Picasso.

Remove the Stoney Ridge monotonic timer code and rely on the TSC.

Modify the calculation used in Family 15h of finding the number
of boost states first, and get the frequency directly out of the
Pstate0 register.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I909743483309279eb8c3bf68852d6082381f0dff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-09 22:20:08 +00:00
Marshall Dawson ba2533f0ee soc/amd/common/lpc: Add decode disable function
It is already trivial to set D14F3x44 to 0, but add a function to wipe
both that and the settings in D14F3x48, along with x48's associated
addresses.

Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-09 22:19:33 +00:00
Marshall Dawson 5aacda4b98 soc/amd/common: Add missing stdint.h to lpc.h
Include the file containing the typedefs for uint_*.

Change-Id: If33765b6dc4236c4b38860bfc4f2cef9b226b81d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-09 22:18:43 +00:00
Kyösti Mälkki 6fdb223859 arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0
These platforms return to romstage from FSP only after
already having torn CAR down. A copy of the entire CAR
region is available and discoverable via HOB.

Previously, CBMEM console detected on-the-fly that CAR
migration had happened and relocated cbmem_console_p
accoringlin with car_sync_var(). However, if the CAR_GLOBAL
pointing to another object inside CAR is a relative offset
instead, we have a more generic solution that can be used
with timestamps code as well.

Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35140
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09 22:17:27 +00:00
Kyösti Mälkki 03026a2a7d intel/fsp_broadwell_de: Add early timestamps
Modify intel/fsp_broadwell_de such that timestamp_init() is
before raminit (and CAR teardown of FSP1.0), adding two new
early timestamps while doing so.

Other FSP1.0 platforms fsp_baytrail and fsp_rangeley already
do it this way.

Change-Id: I3b73e4a61622f789a49973a43b21e8028bcb8ca8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35279
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09 20:23:41 +00:00
Kyösti Mälkki 445394e9ab intel/fsp_broadwell_de: Enable CONSOLE_CBMEM by default
In the very early days of FSP 1.0 this did not work so
we kept it disabled.

Change-Id: I8a88be6df335598d4c6007a8b7ff307b293e1f97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-09 13:33:51 +00:00
Sridhar Siricilla a5208f575f soc/intel/common/block/cse: Add helper function heci_send_receive
Aggregate sending and receiving HECI messages into a single function.

TEST=Verified sending and receiving reply HECI message on CML RVP & Hatch board

Change-Id: Ic95239eef8591d3aadf56a857c97f3f1e12b16ac
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35224
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09 13:32:54 +00:00
Subrata Banik 13e902d571 soc/intel/cannonlake: Allow coreboot to handle SPI lockdown
This patch disables FSP-S SPI lockdown UPDs and lets coreboot perform
SPI lockdown (i.e.flash register DLOCK, FLOCKDN, and WRSDIS before
end of post) in ramstage.

BUG=b:138200201
TEST=FSP debug build suggests those UPDs are disable now.

Change-Id: Id7a6b9859e058b9f1ec1bd45d2c388c02b8ac18c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-09 13:31:36 +00:00
Eric Lai aa8d7721d4 lib/spd_bin: Extend DDR4 spd information
From DDR4 SPD spec:

Byte 4 (0x004): SDRAM Density and Banks
Bits [7, 6]:
00 = 0 (no bank groups)
01 = 1 (2 bank groups)
10 = 2 (4 bank groups)
11 = reserved

Bit [5, 4] :
00 = 2 (4 banks)
01 = 3 (8 banks)
All others reserved

Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks.
Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-09 13:30:10 +00:00
Eric Lai d6c2d1df2c mb/google/drallion: modify USB setting
Based on HW schematic to modify USB setting.
Drallion has two type C on left and two type A on right.

BUG=b:138082886
BRANCH=N/A
TEST=N/A

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I925de209635d92ef61ccb9114efebb4b10f30e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-09 13:29:08 +00:00
Maxim Polyakov 59613ee270 mb/asrock/h110m: add missing pci devices to tree
These devices are enabled after initializing in the FSP

Change-Id: I0a15537b6ba56fcf63267641ef2219f24d25d9c4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-09 13:28:22 +00:00
Maxim Polyakov 50f4c5ae33 mb/asrock/h110m: disable unused sata ports
Sets all unused sata ports to disable in the device tree

Note:
  SATA4 and SATA5 are located at the bottom of the board, but there
  is no connector for this. Apparently, a board with an increased
  number of ports is very rare. Perhaps this is a separate variant
  of the Asrock motherboard. For this reason, these ports are also
  disabled

Change-Id: I5b3ad372f1d6607cc7b4a78e3c59d2a5ae1d2cf5
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-09 13:28:08 +00:00
Maxim Polyakov a433da754a mb/asrock/h110m: disable unused serial buses
Disable spi0, i2c0 and i2c1 in the “SerialIoDevMode” register for the
following reasons:

1. when the AMI BIOS is used, these pci devices are disabled in
   lspci.log;
2. there are no pads in the inteltool.log that use the functions of
   these buses

Change-Id: I01ab10eb3fd41e81a1726805247c2b472d72287c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35070
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09 13:27:50 +00:00
Maxim Polyakov 21353baa16 mb/asrock/h110m: remove unsed i2c_voltage settings
The string "register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" was mistakenly
taken from the Intel KBL-RVP8 devicetree.cb. Remove it, since the i2c4
bus is disabled in the "SerialIoDevMode" register

Change-Id: I44ecd5c22efd66b02a2851dc14a1a95421f39a71
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-09 13:27:36 +00:00
Maxim Polyakov 6342c93ee7 mb/asrock/h110m: use VR_CFG_AMP() macro to set PSI threshold
Change-Id: Iafeb7f7689a16d3b16eb0564c4dd72919a8d1382
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-09 13:27:21 +00:00
Maxim Polyakov a546f11c6d mb/asrock/h110m: fix VR domains configuration
1) VR domains current limit Icc max for Sky/Kaby Lake S is set based
on the processor TDP [1]. Updates information about this

2) Sets VR voltage limit to 1.52V, as described in the datasheets [2,3]

[1] Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde
[2] page 112-119, 6th Generation Intel(R) Processor Families
    for S-Platforms, Volume 1 of 2, Datasheet, August 2018.
    Document Number: 332687-008EN
[3] 7th Generation Intel(R) Processor Families for S Platforms and
    Intel(R) Core(TM) X-Series Processor Family Datasheet, Volume 1,
    December 2018, Document Number: 335195-003

Change-Id: I6e1aefde135ffce75a5d837348595aa20aff0513
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-09 13:27:06 +00:00
Michał Żygowski 033435b75f src/southbridge/amd/pi/hudson/lpc.c: add missing MCFG ACPI table generation
The MCFG ACPI table was not being created.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35bdefb2a565d18917a2f6517d443890f93bd252
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-09 13:25:40 +00:00
Bora Guvendik c42ef561a0 soc/intel/cannonlake: Add ability to disable Heci1
Decide if HECI1 should be hidden prior to boot to OS.

BUG=none
TEST=Boot to OS, verify if Heci1 is disabled on hatch system
     using FSP 1344.

Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-09-09 13:10:33 +00:00
Marshall Dawson 22d66efe65 drivers/intel/fsp2_0: Fix minor whitespace
Change-Id: I03a62c6a35053b67bfc609a365068cf284bcc1a0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35265
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09 07:34:02 +00:00
Kyösti Mälkki c9871505f1 intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK
The documentation for StackBase and StackSize in FSPM_ARCH_UPD is
confusing. Previously the region was shared for heap and stack,
starting with FSP2.1 only for heap (or 'temporary RAM') for HOBs.

Moving the allocation outside DCACHE_BSP_STACK_SIZE allows use of
stack guards and reduces amount of reserved CAR for bootblock and
verstage, as the new allocation in .bss is only taken in romstage.

BUG=b:140268415

Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-09 07:33:18 +00:00
Jacob Garber c563d34fc1 security/tpm: Use correct hash digest lengths
TPMU_HA is a union of all the different hash digests, and so
sizeof(TPMU_HA) evaluates to 64 (the size of the largest one). This will
lead to out-of-bounds writes when copying smaller digests, so use the
specific digest size for each algorithm.

Change-Id: Ic9101f157d5a19836b200ecd99f060de552498d2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 14049{49,50,51,52,53,54,55,56,57,58,60,61,62}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-09-07 01:02:43 +00:00
Ronak Kanabar 5f1786fc9c src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344
Cq-Depend: chrome-internal:1759167
Change-Id: Ib5784eb8c0f7c6e56950dad5c8254e00aa73cef4
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35245
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06 19:23:12 +00:00
Marshall Dawson 7e1f1a5130 soc/amd/common: Add missing stdint.h to acpimmio.h
Include the file containing the typedefs for uint_*.

Change-Id: I3eae80a677e9d6932dc115523da2c0819a371fa7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35268
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06 17:48:19 +00:00
Marshall Dawson b90a2ff079 soc/amd/common: Add missing stdint.h to BiosCallOuts.h
Include the file containing the typedefs for uint_*.

Change-Id: Ib0eea9bfd0c8d9e3eba257b561980accf5b4bab4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35267
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06 17:47:52 +00:00
Felix Held 464f83454f superio/smsc/lpc47b397: fix regression in ops override
b0d868e8fe introduced a regression

Change-Id: I231888f2702027a80f25eb418c4e4703e55db920
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marcello Sylvester Bauer <sylvblck@sylv.io>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-06 17:43:04 +00:00
Christian Walter a8a9fb08dd src/superio/aspeed/ast2400: Use new SuperIO acpigen
Use the new SuperIO ACPI generator to make includes in DSDT obsolete.

Manually tested on X11SSH-TF and verified that ACPI tables are correct.

Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33253
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06 17:38:42 +00:00
Maxim Polyakov 571d07d45b soc/intel/skylake: Add Lewisburg family PCH support
This patch adds Lewisburg C62x Series PCH support by adding the
Production and Super SKUs of the following PCI devices:

 - LPC or eSPI Controllers,
 - PCI Express Root Ports,
 - SSATA and SATA Controllers,
 - SMBus,
 - SPI Controller,
 - ME/HECI,
 - Audio,
 - P2SB,
 - Power Management Controller.

These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US

Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-09-06 15:32:33 +00:00
Frans Hendriks aa771cb19f security/tpm/tss/tcg-2.0: Add support for algorithms
Function marshal_TPMT_HA() supports SHA-256 only.
Add support for more algorithms.

BUG=N/A
TEST=Build binary and verified logging on Facebook FBG-1701

Change-Id: Ife8d44484c7a7cb717035e5ae0870bbee205661b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35276
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06 15:32:10 +00:00
Patrick Rudolph c162131d00 superio/common: Add ssdtgen for generic SuperIOs
Add a generic SuperIO ACPI generator, dropping the need to include
additional code in DSDT for SuperIO.

It generates a device HID based on the decoded I/O range.

Tested on Supermicro X11SSH-TF using AST2400.
The SSDT contains no errors and all devices are present.

Possible TODOs:
* Add "enter config" and "exit config" bytes
* Generate support methods to enter and exit config mode
* Generate support methods to query, change or disable current
  resource settings on specific LDNs

Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-06 15:31:06 +00:00
Changqi Hu 6b2a54030f soc/mediatek: Fix USB enumeration issue
Some USB 3.0 devices fail to be enumerated after USB reset, and xhci
port status register shows the device is disconnected. After measuring
the USB signal, we found that the USB disconnect threshold was lower and
that the disconnect event was triggered unexpectedly.

USB designers suggest changing discth to 15.

BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage

Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu <changqi.hu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-06 15:30:43 +00:00
Frank_Chu 1b439d9ced mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2
Applying first tuned DPTF parameters and TDP PL1/PL2 values for helios.

BUG=b:138752455
BRANCH=none
TEST=emerge-hatch coreboot chromeos-bootimage

Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-09-06 07:01:00 +00:00
Kyösti Mälkki 5e2a2cd5e7 util/sconfig: Expose usable PCI and PNP device names
These devices can be accessed directly by symbolname,
without a search and walk through the tree, as they
have static paths.

Change-Id: I711058f5c809fa9bc7ea4333aaebad6847ebdfd4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31933
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06 00:18:29 +00:00
Arthur Heymans 8bb2bace86 nb/intel/x4x/raminit: Move dummy reads after JEDEC init
Vendor only does dummy reads right after JEDEC init is finished
and dram init was marked as finished.

Dummy reads also make much more sense after JEDEC init as a way to
send a few JEDEC commands, presumably as a way to make sure it is
ready.

TESTED on ga-g41m-es2l (still boots fine)

Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-06 00:15:02 +00:00
Wisley Chen 66922d05d7 mb/google/octopus: Set sar file name for meep sku
Set meep sar file name by sku number

Cq-Depend: chromium:1768380
BUG=b:138261454, b:118782854
BRANCH=octopus
TEST=emerge-octopus coreboot, and check wifi_sar-meep.hex

Change-Id: I25aa3080392ce277e537c973088dde569246630e
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35211
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-05 15:00:14 +00:00
Maxim Polyakov 1317689066 inteltool: Add Skylake Xeon E DMI3 Host bridge Id
Tested on Intel S2600WF and SUPERMICRO MBD-X11DPL-I-O

Change-Id: I4b429536fc2db16d770120487e4c383da437593a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-05 15:00:04 +00:00
Eric Lai 940fb57c06 mb/google/drallion: modify PCIE setting
Based on HW schematic to modify PCIE setting.

BUG=b:138082886
BRANCH=N/A
TEST=N/A

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-05 14:59:38 +00:00
Maxim Polyakov b89ce2e1b4 inteltool: add Lewisburg C62x GPIOs support
These changes are in accordance with the documentation:
[*] page 361, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US

Tested on SUPERMICRO MBD-X11DPL-I-O and Intel S2600WF Wolf Pass

Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-05 14:59:09 +00:00